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IDT5V994DA PDF预览

IDT5V994DA

更新时间: 2024-11-12 12:59:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
9页 71K
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IDT5V994DA 数据手册

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3.3V PROGRAMMABLE  
IDT5V994  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ PLUS  
FEATURES:  
DESCRIPTION  
• Ref input is 5V tolerant  
TheIDT5V994isahighfanout3.3VPLLbasedclockdriverintendedfor  
highperformancecomputinganddata-communicationsapplications.Akey  
featureoftheprogrammableskewistheabilityofoutputstoleadorlagthe  
REFinputsignal. TheIDT5V994haseightprogrammableskewoutputsin  
fourbanksof2.Skewiscontrolledby3-levelinputsignalsthatmaybehard-  
wired to appropriate HIGH-MID-LOW levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency: 17.5MHz to 133MHz  
• Output frequency: 17.5MHz to 133MHz  
• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)  
• 3-level inputs for skew control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.  
However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are  
synchronously disabled.  
Furthermore, whenthePEisheldhigh, alltheoutputsaresynchronized  
with the positive edge of the REF clock input. When PE is held low, all the  
outputs are synchronized with the negative edge of REF. The IDT5V994  
has LVTTL outputs with 12mA balanced drive outputs.  
• Low Jitter: <200ps cycle-to-cycle  
• Available in PLCC and TQFP packages  
FUNCTIONALBLOCKDIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
PE TEST  
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
2F1:0  
3F1:0  
4F1:0  
FB  
3Q0  
3Q1  
Skew  
Select  
3
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
AUGUST 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC 5828/4  

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