Datasheet > IDT5V9955

IDT5V9955

更新时间： 2024-09-23 22:55:27

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
11页	130K
描述
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

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IDT5V9955 数据手册

IDT5V9955

INDUSTRIALTEMPERATURERANGE

3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW

3.3V PROGRAMMABLE

SKEW DUAL PLL CLOCK

DRIVER TURBOCLOCK™ W

IDT5V9955

FEATURES:

DESCRIPTION

• Ref input is 5V tolerant

The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended

forhighperformancecomputinganddata-communicationsapplications.A

keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag

the REF input signal. The IDT5V9955 has sixteen programmable skew

outputs in eight banks of 2. The two separate PLLs allow the user to

independently control A and B banks. Skew is controlled by 3-level input

signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

The feedback input allows divide-by-functionality from 1 to 12 through

the use of the xDS[1:0] inputs. This provides the user with frequency

multiplication from 1 to 12 without using divided outputs for feedback.

WhenthexsOEpinisheldlow, allthexbankoutputsaresynchronously

enabled. However, ifxsOEisheldhigh, allthexbankoutputsexceptx2Q0

and x2Q1 are synchronously disabled. The xLOCK is high when the

xbank PLL has achieved phase lock.

• 8 pairs of programmable skew outputs

• Two separate A and B banks for individual control

• Low skew: 185ps same pair, 250ps same bank, 350ps both

banks

• Selectable positive or negative edge synchronization on each

bank: excellent for DSP applications

• Synchronous output enable on each bank

• Input frequency: 2MHz to 200MHz

• Output frequency: 6MHz to 200MHz

• 3-level inputs for skew and PLL range control

• 3-level inputs for feedback divide selection multiply / divide

ratios of (1-6, 8, 10, 12) / (2, 4)

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <100ps cycle-to-cycle

• Power-down mode on each bank

• Lock indicator on each bank

Furthermore, when xPE is held high, all the outputs are synchronized

withthepositiveedgeoftheREFclockinput. WhenxPEisheldlow, allthe

xbank outputs are synchronized with the negative edge of REF. The

IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.

• Available in BGA package

FUNCTIONALBLOCKDIAGRAM

BLOCK

BPE

BFS

ALOCK

APE

AFS

TEST

REF

BPD

APD

BsOE

AsOE

PLL

/ N

BFB

AFB

BDS1:0

ADS1:0

A1F1:0

B1Q0

B1Q1

A1Q0

A1Q1

Skew

Select

B1F1:0

B2F1:0

B3F1:0

B4F1:0

Select

B2Q0

B2Q1

A2Q0

A2Q1

Skew

Select

Skew

Select

A2F1:0

A3F1:0

A4F1:0

B3Q0

B3Q1

A3Q0

A3Q1

Skew

Select

Skew

Select

B4Q0

B4Q1

A4Q0

A4Q1

Skew

Select

Skew

Select

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2002

2002 Integrated Device Technology, Inc.

DSC 5974/9

12 3 4 5 6 7...11

中文翻译

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与IDT5V9955相关器件

型号	品牌	获取价格	描述	数据表
IDT5V9955BFGI	IDT	获取价格	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, GREEN,
IDT5V9955BFGI8	IDT	获取价格	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, GREEN,
IDT5V9955BFI	IDT	获取价格	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52
IDT5V9955BFI8	IDT	获取价格	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52
IDT5V995PFGI	IDT	获取价格	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
IDT5V995PFGI8	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP44, TQFP-44
IDT5V995PFI	IDT	获取价格	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
IDT60ALVCH16823PA	IDT	获取价格	3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
IDT60LVC162374APA	IDT	获取价格	3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
IDT60LVC162374APF	IDT	获取价格	3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

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