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IDT5V9955BFI8 PDF预览

IDT5V9955BFI8

更新时间: 2024-11-12 21:10:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
11页 124K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52

IDT5V9955BFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA, BGA96,6X16,32针数:96
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92系列:5V
输入调节:STANDARDJESD-30 代码:R-PBGA-B96
JESD-609代码:e0长度:13.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:3功能数量:2
反相输出次数:端子数量:96
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA96,6X16,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:1.5 mm子类别:Clock Driver
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:5.5 mm最小 fmax:200 MHz
Base Number Matches:1

IDT5V9955BFI8 数据手册

 浏览型号IDT5V9955BFI8的Datasheet PDF文件第2页浏览型号IDT5V9955BFI8的Datasheet PDF文件第3页浏览型号IDT5V9955BFI8的Datasheet PDF文件第4页浏览型号IDT5V9955BFI8的Datasheet PDF文件第5页浏览型号IDT5V9955BFI8的Datasheet PDF文件第6页浏览型号IDT5V9955BFI8的Datasheet PDF文件第7页 
3.3V PROGRAMMABLE  
SKEW DUAL PLL CLOCK  
DRIVER TURBOCLOCK™ W  
IDT5V9955  
FEATURES:  
DESCRIPTION  
• Ref input is 5V tolerant  
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
the REF input signal. The IDT5V9955 has sixteen programmable skew  
outputs in eight banks of 2. The two separate PLLs allow the user to  
independently control A and B banks. Skew is controlled by 3-level input  
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.  
The feedback input allows divide-by-functionality from 1 to 12 through  
the use of the xDS[1:0] inputs. This provides the user with frequency  
multiplication from 1 to 12 without using divided outputs for feedback.  
WhenthexsOEpinisheldlow, allthexbankoutputsaresynchronously  
enabled. However, ifxsOEisheldhigh, allthexbankoutputsexceptx2Q0  
and x2Q1 are synchronously disabled. The xLOCK is high when the  
xbank PLL has achieved phase lock.  
• 8 pairs of programmable skew outputs  
• Two separate A and B banks for individual control  
• Low skew: 185ps same pair, 250ps same bank, 350ps both  
banks  
• Selectable positive or negative edge synchronization on each  
bank: excellent for DSP applications  
• Synchronous output enable on each bank  
• Input frequency: 2MHz to 200MHz  
• Output frequency: 6MHz to 200MHz  
• 3-level inputs for skew and PLL range control  
• 3-level inputs for feedback divide selection multiply / divide  
ratios of (1-6, 8, 10, 12) / (2, 4)  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Power-down mode on each bank  
• Lock indicator on each bank  
Furthermore, when xPE is held high, all the outputs are synchronized  
withthepositiveedgeoftheREFclockinput. WhenxPEisheldlow, allthe  
xbank outputs are synchronized with the negative edge of REF. The  
IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.  
• Available in BGA package  
FUNCTIONALBLOCKDIAGRAM  
BLOCK  
BPE  
BFS  
ALOCK  
APE  
AFS  
TEST  
REF  
BPD  
APD  
BsOE  
AsOE  
3
3
3
3
PLL  
PLL  
/ N  
/ N  
BFB  
AFB  
3
3
3
3
BDS1:0  
ADS1:0  
A1F1:0  
B1Q0  
B1Q1  
3
3
A1Q0  
A1Q1  
3
3
Skew  
Skew  
Select  
B1F1:0  
B2F1:0  
B3F1:0  
B4F1:0  
Select  
3
3
B2Q0  
B2Q1  
A2Q0  
A2Q1  
3
3
Skew  
Select  
Skew  
Select  
A2F1:0  
A3F1:0  
A4F1:0  
3
3
3
3
B3Q0  
B3Q1  
A3Q0  
A3Q1  
Skew  
Select  
Skew  
Select  
3
3
B4Q0  
B4Q1  
A4Q0  
A4Q1  
3
3
Skew  
Select  
Skew  
Select  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC 5974/9  

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