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IDT5V994PFGI8 PDF预览

IDT5V994PFGI8

更新时间: 2024-11-12 18:41:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 84K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32

IDT5V994PFGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.76输入调节:STANDARD
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):1.2 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:133 MHz
Base Number Matches:1

IDT5V994PFGI8 数据手册

 浏览型号IDT5V994PFGI8的Datasheet PDF文件第2页浏览型号IDT5V994PFGI8的Datasheet PDF文件第3页浏览型号IDT5V994PFGI8的Datasheet PDF文件第4页浏览型号IDT5V994PFGI8的Datasheet PDF文件第5页浏览型号IDT5V994PFGI8的Datasheet PDF文件第6页浏览型号IDT5V994PFGI8的Datasheet PDF文件第7页 
3.3V PROGRAMMABLE  
IDT5V994  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ PLUS  
FEATURES:  
DESCRIPTION  
• Ref input is 5V tolerant  
TheIDT5V994is ahighfanout3.3VPLLbasedclockdriverintendedfor  
highperformancecomputinganddata-communicationsapplications.Akey  
featureoftheprogrammableskewis theabilityofoutputs toleadorlagthe  
REFinputsignal.TheIDT5V994has eightprogrammableskewoutputs in  
fourbanksof2.Skewiscontrolledby3-levelinputsignalsthatmaybehard-  
wired to appropriate HIGH-MID-LOW levels.  
• 4 pairs of programmable skew outputs  
Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
Input frequency: 17.5MHz to 133MHz  
• Output frequency: 17.5MHz to 133MHz  
• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)  
• 3-level inputs for skew control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.  
However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are  
synchronouslydisabled.  
Furthermore,whenthePEis heldhigh,alltheoutputs aresynchronized  
withthe positive edge ofthe REFclockinput.WhenPEis heldlow,allthe  
outputs are synchronizedwiththe negative edge ofREF. The IDT5V994  
has LVTTLoutputs with12mAbalanceddrive outputs.  
Low Jitter: <200ps cycle-to-cycle  
Available in PLCC and TQFP packages  
FUNCTIONALBLOCKDIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
3
3
1F1:0  
2F1:0  
3F1:0  
4F1:0  
PE TEST  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC 5828/6  

IDT5V994PFGI8 替代型号

型号 品牌 替代类型 描述 数据表
IDT5V994PFGI IDT

完全替代

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM PLUS
5V994PFGI8 IDT

类似代替

PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32

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