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ICS9FG1201H

更新时间: 2024-11-07 03:14:31
品牌 Logo 应用领域
艾迪悌 - IDT PC时钟
页数 文件大小 规格书
21页 265K
描述
Frequency Generator for CPU, PCIe Gen1 & Fully Buffered DIMM Clocks

ICS9FG1201H 数据手册

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DATASHEET  
ICS9FG1201H  
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered  
DIMM Clocks  
Description  
Features/Benefits  
ICS9FG1201 follows the Intel DB1200G Differential Buffer  
Specification. This buffer provides 12 output clocks for CPU Host  
Bus, PCI Express, or Fully Buffered DIMM applications.The outputs  
are configured with two groups. Both groups (DIF 9:0) and (DIF  
11:10) can be equal to or have a gear ratio to the input clock. A  
differential CPU clock from a CK410 or CK410B main clock generator,  
such as the ICS954101 or ICS932S401, drives the ICS9FG1201.  
ICS9FG1201 can provide outputs up to 400MHz.  
Power up default is all outputs in 1:1 mode  
DIF_(9:0) can be “gear-shifted” from the input CPU Host  
Clock  
DIF_(11:10) can be “gear-shifted” from the input CPU Host  
Clock  
Spread spectrum compatible  
Supports output clock frequencies up to 400 MHz  
8 Selectable SMBus addresses  
SMBus address determines PLL or Bypass mode  
Key Specifications  
DIF output cycle-to-cycle jitter < 50ps  
DIF output-to-output skew < 50ps within a group  
DIF output-to-output skew < 100ns across all outputs  
56-pin SSOP/TSSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
OE#  
SPREAD  
COMPATIBLE  
PLL  
GEAR  
SHIFT  
LOGIC  
2
STOP  
LOGIC  
DIF(11:10)  
10  
OE(9:0)#  
SPREAD  
COMPATIBLE  
PLL  
GEAR  
SHIFT  
LOGIC  
CLK_IN  
10  
STOP  
LOGIC  
DIF(9:0)  
CLK_IN#  
HIGH_BW#  
FS_A_410  
VTT_PWRGD#/PD  
SMB_A0  
SMB_A1  
CONTROL  
LOGIC  
SMB_A2_PLLBYP#  
SMBDAT  
SMBCLK  
IREF  
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks  
ICS9FG1201H 10/22/07  
1

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