5秒后页面跳转
ICS9FG1901YK-T PDF预览

ICS9FG1901YK-T

更新时间: 2024-09-24 19:45:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路
页数 文件大小 规格书
19页 263K
描述
Processor Specific Clock Generator, 400MHz, PQCC72, PLASTIC, MO-220, MLF-72

ICS9FG1901YK-T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:72
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.87
JESD-30 代码:S-PQCC-N72JESD-609代码:e0
长度:10 mm端子数量:72
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS9FG1901YK-T 数据手册

 浏览型号ICS9FG1901YK-T的Datasheet PDF文件第2页浏览型号ICS9FG1901YK-T的Datasheet PDF文件第3页浏览型号ICS9FG1901YK-T的Datasheet PDF文件第4页浏览型号ICS9FG1901YK-T的Datasheet PDF文件第5页浏览型号ICS9FG1901YK-T的Datasheet PDF文件第6页浏览型号ICS9FG1901YK-T的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS9FG1901  
Systems, Inc.  
Frequency Generator for P4CPU, PCI Express& Fully Buffered DIMM Clocks  
Functionality at Power Up (PLL Mode)  
Recommended Application:  
CLK_IN (CPU FSB)  
MHz  
DIF_(18:0)  
DB1900G: CPU Host Bus, PCI Express and Fully-Buffered  
DIMM clocking  
FS_A_4101  
MHz  
1
0
100 <= CLK_IN < 200  
200<= CLK_IN <= 400  
CLK_IN  
CLK_IN  
Features:  
Power up default is all outputs in 1:1 mode  
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for  
correct values.  
DIF_(16:0) can be “gear-shifted” from the input CPU  
Host Clock  
DIF_(18:17) can be “gear-shifted” from the input CPU  
Host Clock  
Power Down Functionality  
Spread spectrum compatible  
Supports output clock frequencies up to 400 MHz  
8 Selectable SMBus addresses  
INPUTS  
OUTPUTS  
PLL State  
VDDA/PD# CLK_IN/CLK_IN# DIF DIF#  
Running  
Hi-Z  
3.3V (NOM)  
GND  
Running  
X
ON  
OFF  
SMBus address determines PLL or Bypass mode  
VDDA controlled power down mode  
Functionality Note  
It is recommended that Byte 2, bit 6 be toggled from 1 to 0  
and back to 1, the first time VDDA is applied. This ensures  
proper initialization of the device.  
Key Specifications:  
DIF output cycle-to-cycle jitter < 50ps  
DIF (0:18) output-to-output skew < 225ps  
DIF (0:16) output-to-output skew < 100ps  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
IREF  
GNDA  
VDDA/PD#  
HIGH_BW#  
FS_A_410  
DIF_0  
1
2
3
4
5
6
7
8
9
54 OE14#  
53 DIF_13#  
52 DIF_13  
51 OE13#  
50 DIF_12#  
49 DIF_12  
48 OE12#  
DIF_0#  
DIF_1  
DIF_1#  
GND 10  
VDD 11  
DIF_2 12  
DIF_2# 13  
DIF_3 14  
DIF_3# 15  
DIF_4 16  
47  
46  
VDD  
GND  
ICS9FG1901  
45 DIF_11#  
44 DIF_11  
43 OE11#  
42 DIF_10#  
41 DIF_10  
40 OE10#  
39 DIF_9#  
38 DIF_9  
DIF_4# 17  
OE_01234# 18  
37 OE9#  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin MLF  
0962E—01/02/07  
Other names and brands may be claimed as the property of others.  

与ICS9FG1901YK-T相关器件

型号 品牌 获取价格 描述 数据表
ICS9FG1904B-1 ICSI

获取价格

Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
ICS9FG1904BK-1LF IDT

获取价格

Clock Generator, PQCC72
ICS9FG1904BK-1LFT ICSI

获取价格

Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
ICS9LP505-1HGLF IDT

获取价格

PC MAIN CLOCK
ICS9LP525-2 IDT

获取价格

56-pin CK505 for Intel Desktop Systems
ICS9LPR426A ICSI

获取价格

Low Power Programmable Timing Control Hub⑩ fo
ICS9LPR501 ICSI

获取价格

64-pin CK505 w/Fully Integrated Voltage Regulator
ICS9LPR501 IDT

获取价格

64-pin CK505 w/Fully Integrated Voltage Regulator
ICS9LPR501_09 IDT

获取价格

64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
ICS9LPR501HGLF IDT

获取价格

Microprocessor Circuit, PDSO64