Datasheet > ICS9LPR501

ICS9LPR501

更新时间： 2024-11-07 04:44:23

品牌	Logo	应用领域
艾迪悌 - IDT		稳压器
页数	文件大小	规格书
22页	237K
描述
64-pin CK505 w/Fully Integrated Voltage Regulator

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中文翻译

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数据手册

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ICS9LPR501 数据手册

Integrated

Circuit

ICS9LPR501

Systems, Inc.

64-pin CK505 w/Fully Integrated Voltage Regulator

Pin Configuration

Recommended Application:

CK505 compliant clock with fully integrated voltage regulator

PCI0/CR#_A 1

VDDPCI 2

64 SCLK

63 SDATA

PCI1/CR#_B 3

PCI2/TME 4

62 REF0/FSLC/TEST_SEL

61 VDDREF

60 X1

59 X2

58 GNDREF

57 FSLB/TEST_MODE

56 CK_PWRGD/PD#

55 VDDCPU

54 CPUT0

53 CPUC0

52 GNDCPU

51 CPUT1_F

50 CPUC1_F

49 VDDCPU_IO

48 NC

47 CPUT2_ITP/SRCT8

46 CPUC2_ITP/SRCC8

45 VDDSRC_IO

44 SRCT7/CR#_F

43 SRCC7/CR#_E

42 GNDSRC

Output Features:

•

2 - CPU differential low power push-pull pairs

10 - SRC differential low power push-pull pairs

1 - CPU/SRC selectable differential low power push-pull

pair

PCI3 5

PCI4/SRC5_EN 6

PCI_F5/ITP_EN 7

GNDPCI 8

VDD48 9

USB_48MHz/FSLA 10

GND48 11

VDD96_IO 12

DOTT_96/SRCT0 13

DOTC_96/SRCC0 14

GND 15

•

1 - SRC/DOT selectable differential low power push-pull

pair

•

5 - PCI, 33MHz

1 - PCI_F, 33MHz free running

1 - USB, 48MHz

1 - REF, 14.318MHz

VDD 16

SRCT1/SE1 17

SRCC1/SE2 18

GND 19

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

SRC output cycle-cycle jitter < 125ps

PCI outputs cycle-cycle jitter < 250ps

+/- 100ppm frequency accuracy on CPU & SRC clocks

VDDPLL3_IO 20

SRCT2/SATAT 21

SRCC2/SATAC 22

GNDSRC 23

SRCT3/CR#_C 24

SRCC3/CR#_D 25

VDDSRC_IO 26

SRCT4 27

41 SRCT6

40 SRCC6

39 VDDSRC

38 PCI_STOP#/SRCT5

37 CPU_STOP#/SRCC5

36 VDDSRC_IO

35 SRCC10

Features/Benefits:

•

Does not require external pass transistor for voltage

regulator

SRCC4 28

GNDSRC 29

SRCT9 30

•

Supports spread spectrum modulation, default is 0.5%

down spread

SRCC9 31

SRCC11/CR#_G 32

34 SRCT10

33 SRCT11/CR#_H

•

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

64-pin TSSOP

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

Selectable between one SRC differential push-pull pair

and two single-ended outputs

Table 1: CPU Frequency Select Table

FS_LC²

B0b7

FS_LB¹

B0b6

FS_LA¹

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

266.66

133.33

200.00

166.66

333.33

100.00

400.00

100.00

33.33 14.318 48.00

Reserved

96.00

1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS}and V_{IH_FS}specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS_LC is a three-level input. Please see the V_{IL_FS}and V_{IH_FS}

specifications in the Input/Supply/Common Output Parameters Table for correct values.

1118F—11/06/07

12 3 4 5 6 7...22

中文翻译

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与ICS9LPR501相关器件

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ICS9LPR501_09	IDT	获取价格	64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
ICS9LPR501HGLF	IDT	获取价格	Microprocessor Circuit, PDSO64
ICS9LPR501HGLFT	IDT	获取价格	Microprocessor Circuit, PDSO64
ICS9LPR501YGLFT	IDT	获取价格	64-pin CK505 w/Fully Integrated Voltage Regulator
ICS9LPR501YGLFT	ICSI	获取价格	64-pin CK505 w/Fully Integrated Voltage Regulator
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