Datasheet > ICS9LPRS502

ICS9LPRS502

更新时间： 2024-01-18 05:40:53

品牌	Logo	应用领域
艾迪悌 - IDT		稳压器
页数	文件大小	规格书
29页	285K
描述
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ICS9LPRS502 数据手册

Datasheet

ICS9LPRS502

56-PIN CK505 W/FULLY INTEGRATED VOLTAGE

REGULATOR + INTEGRATED SERIES RESISTOR

Recommended Application:

CK505 compliant clock with fully integrated voltage

regulator and Internal series resistor on differential outputs,

PCIe Gen 1 compliant

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

SRC output cycle-cycle jitter < 125ps

PCI outputs cycle-cycle jitter < 250ps

+/- 100ppm frequency accuracy on CPU & SRC

clocks

Output Features:

•

2 - CPU differential low power push-pull pairs

7 - SRC differential low power push-pull pairs

Features/Benefits:

1 - CPU/SRC selectable differential low power push-pull

pair

•

Does not require external pass transistor for voltage

regulator

•

1 - SRC/DOT selectable differential low power push-pull

pair

•

Integrated series resistors on differential outputs,

Z_o=50W

•

5 - PCI, 33MHz

Supports spread spectrum modulation, default is 0.5%

down spread

1 - PCI_F, 33MHz free running

1 - USB, 48MHz

Uses external 14.318MHz crystal, external crystal

load caps are required for frequency tuning

1 - REF, 14.318MHz

One differential push-pull pair selectable between

SRC and two single-ended outputs

Table 1: CPU Frequency Select Table

Pin Configuration

FS_LC²FS_LB¹FS_LA¹

PCICLK0/CR#_A 1

VDDPCI 2

56 SCLK

55 SDATA

54 FSLC/TEST_SEL/REF0

53 VDDREF

52 X1

51 X2

50 GNDREF

49 FSLB/TEST_MODE

48 CK_PWRGD/PD#

47 VDDCPU

46 CPUCLKT0

45 CPUCLKC0

44 GNDCPU

43 CPUCLKT1

42 CPUCLKC1

41 VDDCPUI/O

CPU

SRC

PCI

REF

USB

MHz

DOT

MHz

B0b7

B0b6

B0b5

PCICLK1/CR#_B 3

PCICLK2/LTE 4

PCICLK3 5

PCICLK4/SRC5_EN 6

PCI_F5/ITP_EN 7

GNDPCI 8

VDD48 9

USB_48MHz/FSLA 10

GND48 11

266.66

133.33

200.00

166.66

333.33

100.00

400.00

100.00

33.33 14.318 48.00

Reserved

96.00

VDD96I/O 12

1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS}and V_{IH_FS}specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

DOTT_96/SRCCLKT0 13

DOTC_96/SRCCLKC0 14

GND 15

2. FS_LC is a three-level input. Please see the V_{IL_FS}and V_{IH_FS}

VDD 16

specifications in the Input/Supply/Common Output Parameters Table for correct values.

40 NC

SRCCLKT1/SE1

SRCCLKC1/SE2 18

GND 19

39 CPUCLKT2_ITP/SRCCLKT8

38 CPUCLKC2_ITP/SRCCLKC8

37 VDDSRCI/O

VDDPLL3I/O 20

SRCCLKT2/SATACLKT 21

SRCCLKC2/SATACLKC 22

GNDSRC 23

36 SRCCLKT7/CR#_F

35 SRCCLKC7/CR#_E

34 GNDSRC

SRCCLKT3/CR#_C 24

SRCCLKC3/CR#_D 25

VDDSRCI/O 26

33 SRCCLKT6

32 SRCCLKC6

31 VDDSRC

SRCCLKT4 27

SRCCLKC4 28

30 PCI_STOP#/SRCCLKT5

29 CPU_STOP#/SRCCLKC5

56-SSOP/TSSOP

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

IDT^TM/ICS^TM56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1125E—02/26/09

12 3 4 5 6 7...29

中文翻译

下载PDF

与ICS9LPRS502相关器件

型号	品牌	获取价格	描述	数据表
ICS9LPRS511EGLF	IDT	获取价格	Low Power Programmable Timing Control Hubâ¢
ICS9LPRS525	IDT	获取价格	56-pin CK505 for Intel Systems
ICS9LPRS525_10	IDT	获取价格	56-pin CK505 for Intel Systems
ICS9LPRS525_11	IDT	获取价格	56-pin CK505 for Intel Systems
ICS9LPRS525_1107	IDT	获取价格	56-pin CK505 for Intel Systems
ICS9LPRS535	IDT	获取价格	48-pin CK505 for Intel Systems
ICS9LPRS535_10	IDT	获取价格	48-pin CK505 for Intel Systems
ICS9LPRS545	ICSI	获取价格	48-pin CK505 for Intel Systems
ICS9LRS3187B	IDT	获取价格	PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS
ICS9LRS3197AKLFT	IDT	获取价格	ICS9LRS3197AKLFT

与ICS9LPRS502相关文章

MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

5
PMOS管背靠背连接：串联还是并联？
2024-06-28

5
高压电解电容的分类与选型策略
2024-06-28

6
数码管：基本概念、分类、技术发展及市场趋势
2024-06-27

12

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS9LPRS502

ICS9LPRS502 数据手册

与ICS9LPRS502相关器件

与ICS9LPRS502相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS9LPRS502

ICS9LPRS502 数据手册

与ICS9LPRS502相关器件

与ICS9LPRS502相关文章

您还可以找

您在本页遇到什么问题？