Datasheet > ICS9P935YFLF-T

ICS9P935YFLF-T

更新时间： 2024-09-25 11:14:55

品牌	Logo	应用领域
艾迪悌 - IDT		双倍数据速率
页数	文件大小	规格书
13页	193K
描述
DDR I/DDR II Phase Lock Loop Zero Delay Buffer

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中文翻译

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数据手册

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ICS9P935YFLF-T 数据手册

DATASHEET

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Description

Pin Configuration

DDR I/DDR II Zero Delay Clock Buffer

DDRC0 1

DDRT0 2

VDD2.5/1.8 3

DDRT1 4

28 GND

27 DDRC5

26 DDRT5

25 VDD2.5/1.8

24 GND

23 DDRC4

22 DDRT4

21 VDD2.5/1.8

20 SDATA

19 SCLK

Output Features

•

Low skew, low jitter PLL clock driver

Max frequency supported = 400MHz (DDRII 800)

DDRC1 5

I²C for functional and output control

GND 6

VDDA2.5/1.8 7

GND 8

CLK_INT 9

CLK_INC 10

VDD2.5/1.8 11

DDRT2 12

DDRC2 13

GND 14

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

•

Programmable skew through SMBus

Frequency defect control thorugh SMBus

Individual output control programmable through SMBus

18 FB_IN

Key Specifications

17 FB_OUT

16 DDRT3

15 DDRC3

•

CYCLE - CYCLE jitter: <100ps

OUTPUT - OUTPUT skew: <100ps

DUTY CYCLE: 48% - 52%

28-pin SSOP package

28-SSOP/TSSOP

•

Available in RoHS compliant packaging

Operates @ 2.5V or 1.8V

Funtional Block Diagram

FB_OUT

Control

Logic

SCLK

DDRT0

DDRC0

SDATA

DDRT1

DDRC1

DDRT2

DDRC2

DDRT3

DDRC3

FB_IN

CLK_INT

CLK_INC

PLL

DDRT4

DDRC4

DDRT5

DDRC5

IDT^TM/ICS^TMDDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H 12/1/08

12 3 4 5 6 7...13

中文翻译

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