Datasheet > ICS9LPRS365BGLFT

ICS9LPRS365BGLFT

更新时间： 2024-11-07 12:28:03

品牌	Logo	应用领域
艾迪悌 - IDT		稳压器
页数	文件大小	规格书
28页	481K
描述
64-pin CK505 w/Fully Integrated Voltage Regulator Integrated Series Resistor

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ICS9LPRS365BGLFT 数据手册

Integrated

Circuit

Systems, Inc.

ICS9LPRS365

Advance Information

64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Recommended Application:

Pin Configuration

PCI0/CR#_A 1

64 SCLK

CK505 compliant clock with fully integrated voltage regulator

and Internal series resistor on differential outputs

VDDPCI 2

PCI1/CR#_B 3

PCI2/TME 4

SDATA

62 REF0/FSLC/TEST_SEL

61 VDDREF

Output Features:

PCI3 5

60 X1

59 X2

58 GNDREF

57 FSLB/TEST_MODE

56 CK_PWRGD/PD#

55 VDDCPU

54 CPUT0

53 CPUC0

52 GNDCPU

51 CPUT1_F

50 CPUC1_F

49 VDDCPU_IO

48 NC

47 CPUT2_ITP/SRCT8

46 CPUC2_ITP/SRCC8

45 VDDSRC_IO

44 SRCT7/CR#_F

43 SRCC7/CR#_E

42 GNDSRC

PCI4/27_Select 6

PCI_F5/ITP_EN 7

GNDPCI 8

•

2 - CPU differential low power push-pull pairs

9 - SRC differential low power push-pull pairs

1 - CPU/SRC selectable differential low power push-pull pair

1 - SRC/DOT selectable differential low power push-pull pair

5 - PCI, 33MHz

1 - PCI_F, 33MHz free running

1 - USB, 48MHz

1 - REF, 14.318MHz

VDD48 9

USB_48MHz/FSLA 10

GND48 11

VDD96_IO 12

SRCT0/DOTT_96 13

SRCC0/DOTC_96 14

GND 15

VDDPLL3 16

27MHz_NonSS/SRCT1/SE1 17

27MHz_SS/SRCC1/SE2 18

GND 19

Key Specifications:

VDDPLL3_IO 20

SRCT2/SATAT 21

SRCC2/SATAC 22

GNDSRC 23

SRCT3/CR#_C 24

SRCC3/CR#_D 25

VDDSRC_IO 26

SRCT4 27

•

CPU outputs cycle-cycle jitter < 85ps

SRC output cycle-cycle jitter < 125ps

PCI outputs cycle-cycle jitter < 250ps

+/- 100ppm frequency accuracy on CPU & SRC clocks

41 SRCT6

40 SRCC6

39 VDDSRC

38 PCI_STOP#

37 CPU_STOP#

36 VDDSRC_IO

35 SRCC10

SRCC4 28

GNDSRC 29

SRCT9 30

SRCC9 31

Features/Benefits:

•

Does not require external pass transistor for voltage

regulator

34 SRCT10

SRCC11/CR#_G 32

33 SRCT11/CR#_H

•

Integrated 33ohm series resistors on differential outputs,

64-TSSOP

Z_o=50Ω

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

•

Supports spread spectrum modulation, default is 0.5% down

spread

•

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

64-TSSOP

27_Select (power on latch)

DOT96, LCD_SS

Byte1 bit7 = 1.

SRC0, 27MHz Non SS & SS

Byte1 bit7 = 0.

Pin13/14 & Pin17/18

Selectable between one SRC differential push-pull pair

and two single-ended outputs

Table 1: CPU Frequency Select Table

FS_LC²

B0b7

FS_LB¹

B0b6

FS_LA¹

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

266.66

133.33

200.00

166.66

333.33

100.00

400.00

100.00

33.33 14.318 48.00

Reserved

96.00

1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS}and V_{IH_FS}specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS_LC is a three-level input. Please see the V_{IL_FS}and V_{IH_FS}

specifications in the Input/Supply/Common Output Parameters Table for correct values.

1218—09/09/09

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

12 3 4 5 6 7...28

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ICS9LPRS501	IDT	获取价格	64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
ICS9LPRS502	IDT	获取价格	56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR

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