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ICS9FG1904B-1 PDF预览

ICS9FG1904B-1

更新时间: 2024-11-07 02:50:59
品牌 Logo 应用领域
矽成 - ICSI PC
页数 文件大小 规格书
22页 222K
描述
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD

ICS9FG1904B-1 数据手册

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Integrated  
Circuit  
ICS9FG1904B-1  
Systems, Inc.  
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD  
RecommendedApplication:  
DB1900GS/GSO with 15:4 output grouping  
Functionality at Power Up (PLL Mode)  
CLK_IN (CPU FSB)  
MHz  
DIF_(18:0)  
MHz  
CLK_IN  
CLK_IN  
FS_A_4101  
Features:  
1
0
100 <= CLK_IN < 200  
200<= CLK_IN <= 400  
Power up default is all outputs in 1:1 mode  
DIF_(14:0) can be “gear-shifted” from the input CPU  
Host Clock  
FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS  
1.  
specifications in the Input/Supply/Common Output Parameters Table for  
correct values.  
DIF_(18:15) can be “gear-shifted” from the input CPU  
Host Clock  
Spread spectrum compatible  
Supports output clock frequencies up to 400 MHz  
8 Selectable SMBus addresses  
Power Down Functionality  
INPUTS  
OUTPUTS  
PLL State  
CKPWRGD/  
CLK_IN/  
CLK_IN#  
Running  
X
SMBus address determines PLL or Bypass mode  
PD#  
1
DIF/DIF#  
Running  
Hi-Z  
ON  
OFF  
0
KeySpecifications:  
DIF output cycle-to-cycle jitter < 50ps  
DIF output-to-output skew < 100ps within a group  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
IREF  
GNDA  
VDDA  
1
2
3
4
5
6
7
8
9
54 OE14#  
53 DIF_13#  
52 DIF_13  
51 OE13#  
50 DIF_12#  
49 DIF_12  
48 OE12#  
47 VDD  
HIGH_BW#  
FS_A_410  
DIF_0  
DIF_0#  
DIF_1  
DIF_1#  
GND 10  
VDD 11  
DIF_2 12  
DIF_2# 13  
DIF_3 14  
DIF_3# 15  
DIF_4 16  
46 GND  
ICS9FG1904-1  
45 DIF_11#  
44 DIF_11  
43 OE11#  
42 DIF_10#  
41 DIF_10  
40 OE10#  
39 DIF_9#  
38 DIF_9  
DIF_4# 17  
OE_01234# 18  
37 OE9#  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin MLF  
1255B—08/03/07  
Other names and brands may be claimed as the property of others.  

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