Datasheet > ICS9DB202CGT

ICS9DB202CGT

更新时间： 2024-11-22 21:54:47

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
11页	263K
描述
Two 0.7V current mode differential HCSL output pairs, 1 differential clock input

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ICS9DB202CGT 数据手册

ICS9DB202

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

™

JITTER

ATTENUATOR

GENERAL DESCRIPTION

Features

The ICS9DB202 is a high perfromance 1-to-2 Dif- • Two 0.7V current mode differential HCSL output pairs

ICS

ferential-to-HCSL Jitter Attenuator designed for use

• 1 differential clock input

HiPerClockS™

in PCI Express™ systems. In some PCI Express™

systems, such as those found in desktop PCs, the

PCI Express™ clocks are generated from a low

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

bandwidth, high phase noise PLL frequency synthesizer.In these

systems, a jitter-attenuating device may be necessary in order

to reduce high frequency random and deterministic jitter com-

ponents from the PLL synthesizer and from the system board.

The ICS9DB202 has two PLL bandwidth modes. In low band-

width mode, the PLL loop bandwidth is 500kHz.This setting of-

fers the best jitter attenuation and is still high enough to pass a

triangular input spread spectrum profile. In high bandwidth mode,

the PLL bandwidth is at 1MHz and allows the PLL to pass more

spread spectrum modulation.

• Maximum output frequency: 140MHz

• Output skew: 110ps (maximum)

• Cycle-to-cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package available

For serdes which have x10 reference multipliers instead of x12.5

multipliers, each of the two PCI Express™ outputs (PCIEX0:1)

can be set for 125MHz instead of 100MHz by configuring the

appropriate frequency select pins (FS0:1).

• Industrial temperature information available upon request

PIN ASSIGNMENT

V^DDA

BYPASS

IREF

FS1

V^DD

PLL_BW

CLK

nCLK

FS0

V^DD

BLOCK DIAGRAM

IREF

Current

Set

GND

PCIEXT1

PCIEXC1

V^DD

PCIEXT0

PCIEXC0

V^DD

1 HiZ

0 Enabled

nOE0

nOE1

nOE0

ICS9DB202

20-LeadTSSOP

6.50mm x 4.40mm x 0.92

package body

PCIEXT0

nPCIEXC0

nCLK

CLK

Loop

Filter

Phase

Detector

0 ÷4

1 ÷5

VCO

G Package

Top View

ICS9DB202

20-Lead, 209-MIL SSOP

5.30mm x 7.20mm x 1.75mm

body package

FS0

÷5

F Package

TopView

Internal Feedback

PCIEXT1

nPCIEXC1

0 ÷5

1 ÷4

FS1

BYPASS

nOE1

1 HiZ

0 Enabled

9DB202CG

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 6, 2004

12 3 4 5 6 7...11

中文翻译

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与ICS9DB202CGT相关器件

型号	品牌	获取价格	描述	数据表
ICS9DB202CK-01	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01LF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01LFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01T	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB206CFLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X
ICS9DB206CFLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X
ICS9DB206CLLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X
ICS9DB206CLLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X
ICS9DB206FT	IDT	获取价格	Clock Driver
ICS9DB206GT	IDT	获取价格	Clock Driver

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