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ICS9DB206YGLFT PDF预览

ICS9DB206YGLFT

更新时间: 2024-11-19 15:34:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 94K
描述
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PDSO28, 0.173 INCH, 0.65 MM PITCH, MO-153, TSSOP-28

ICS9DB206YGLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:0.173 INCH, 0.65 MM PITCH, MO-153, TSSOP-28针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:6
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
Base Number Matches:1

ICS9DB206YGLFT 数据手册

 浏览型号ICS9DB206YGLFT的Datasheet PDF文件第2页浏览型号ICS9DB206YGLFT的Datasheet PDF文件第3页浏览型号ICS9DB206YGLFT的Datasheet PDF文件第4页浏览型号ICS9DB206YGLFT的Datasheet PDF文件第5页浏览型号ICS9DB206YGLFT的Datasheet PDF文件第6页浏览型号ICS9DB206YGLFT的Datasheet PDF文件第7页 
Integrated  
Circuit  
Systems, Inc.  
ICS9DB206  
Advance Information  
Zero Delay Buffer for PCI-Express  
Recommended Application:  
Pin Configuration  
Zero-delay buffer for PCI-Express  
PLL_BW 1  
CLK_INT 2  
CLK_INC 3  
FS0 4  
28 VDDA  
27 GNDA  
26 IREF  
Zero-delay buffer for 0.7V Differential CPU and SATA  
clocks  
25 FS1  
Output Features:  
PCIEXT0 5  
PCIEXC0 6  
VDD 7  
24 PCIEXT5  
23 PCIEXC5  
22 VDD  
6 - 0.7V current mode differential output pairs (HSCL)  
OE pins control output pairs (0:2) and (3:5)  
Output pair 0 always tracks the input frequency  
GND 8  
21 GND  
PCIEXT1 9  
PCIEXC1 10  
PCIEXT2 11  
PCIEXC2 12  
VDD 13  
20 PCIEXT4  
19 PCIEXC4  
18 PCIEXT3  
17 PCIEXC3  
16 VDD  
Key Specifications:  
Cycle-to-cycle jitter < 50ps  
Output-to-output skew < 50 ps  
Features/Benefits:  
OE0 14  
15 OE1  
Supports Serial-ATA  
FS pins allow optional 5/4 multiplication of input  
frequency to give 125 MHz outputs at FIN = 100 MHz  
28-pin SSOP & TSSOP  
Spread Spectrum Compatible  
Adjustable PLL Bandwidth  
Ratio of Output Frequency to Input Frequency  
FS0  
PCIEX0  
PCIEX1  
PCIEX2  
1
1
5/4  
1
5/4  
1
0
1
FS1  
0
PCIEX3  
PCIEX4  
PCIEX5  
1
1
1
5/4  
5/4  
5/4  
1
Output Enable Functionality  
OE0  
0
1
PCIEX(0:2)  
Hi-Z  
Running  
OE1  
0
1
PCIEX(3:5)  
Hi-Z  
Running  
0835—07/24/03  
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.  
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.  

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