Datasheet > ICS9DB306LLFT

ICS9DB306LLFT

更新时间： 2024-11-19 21:16:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	309K
描述
Clock Driver

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技术参数
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ICS9DB306LLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

ICS9DB306LLFT 数据手册

ICS9DB306

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

JITTER

ATTENUATOR

GENERAL DESCRIPTION

Features

The ICS9DB306 is a high performance 1-to-6

• Six differential LVPECL output pairs

• 1 differential clock input

ICS

Differential-to LVPECL Jitter Attenuator designed

for use in PCI Express™ systems. In some PCI

Express™ systems, such as those found in desktop

PCs, the PCI Express™ clocks are generated from

a low bandwidth, high phase noise PLL frequency

HiPerClockS™

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

synthesizer. In these systems, a zero delay buffer may be

required to attenuate high frequency random and deterministic

jitter components from the PLL synthesizer and from the system

board. The ICS9DB306 has 2 PLL bandwidth modes. In low

bandwidth mode, the PLL loop BW is about 500kHz and this

setting will attenuate much of the jitter from the reference clock

input while being high enough to pass a triangular input spread

spectrum profile. There is also a high bandwidth mode which

• Maximum output frequency: 140MHz

• Output skew: 135ps (maximum)

• Cycle-to-Cycle jitter: 25ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

3ps (typical)

sets the PLL bandwidth at 1MHz which will pass more spread • 3.3V operating supply

spectrum modulation.

• 0°C to 70°C ambient operating temperature

For serdes which have x30 reference multipliers instead of x25

multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be

set for 125MHz instead of 100MHz by configuring the appropri-

ate frequency select pins (FS0:1). Output PCIEX0 will always

run at the reference clock frequency (usually 100MHz) in desk-

top PC PCI Express™ Applications.

• Lead-Free package available

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

1 Disabled

nOE0

VEE

PCIEXT1

PCIEXC1

PCIEXT2

PCIEXC2

V^CC

VCC

0 Enabled

PCIEXC0

PCIEXT0

FS0

nCLK

CLK

PLL_BW

V^CCA

VEE

PCIEXT0

nPCIEXC0

÷5

Buffer

nOE0

nOE1

V^CC

CLK

Loop

PCIEXT1

nPCIEXC1

Phase

Detector

BYPASS

FS1

0 ÷4

PCIEXC3

VCO

nCLK

Filter

PCIEXT3

PCIEXC4

PCIEXT4

V^EE

1 ÷5

PCIEXT2

nPCIEXC2

PCIEXT5

PCIEXC5

V^CC

FS0

÷5

ICS9DB306

28-LeadTSSOP, 173-MIL

4.4mm x 9.7mm x 0.92mm

body package

Internal Feedback

PCIEXT3

nPCIEXC3

0 ÷5

1 ÷4

L Package

TopView

PCIEXT4

nPCIEXC4

ICS9DB306

28-Lead, 209-MIL SSOP

5.3mm x 10.2mm x 1.75mm

body package

PCIEXT5

nPCIEXC5

FS1

F Package

TopView

BYPASS

nOE1

1 Disabled

0 Enabled

9DB306BL

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 22, 2004

12 3 4 5 6 7...15

中文翻译

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与ICS9DB306LLFT相关器件

型号	品牌	获取价格	描述	数据表
ICS9DB401	ICSI	获取价格	Four Output Differential Buffer for PCI Express
ICS9DB401BFLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209
ICS9DB401BFLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209
ICS9DB401BGLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 M
ICS9DB401BGLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 M
ICS9DB401C	IDT	获取价格	Four Output Differential Buffer for PCI Express
ICS9DB401CFLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209
ICS9DB401CFLFT	IDT	获取价格	Four Output Differential Buffer for PCI Express
ICS9DB401CGLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.40 X
ICS9DB401CGLFT	IDT	获取价格	Four Output Differential Buffer for PCI Express

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