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ICS9DB202CK-01LF PDF预览

ICS9DB202CK-01LF

更新时间: 2024-11-19 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 342K
描述
PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95 MM HEIGHT, LEAD FREE, MO-220, VFQFN-32

ICS9DB202CK-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:9DB输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:1最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mmBase Number Matches:1

ICS9DB202CK-01LF 数据手册

 浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第2页浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第3页浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第4页浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第5页浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第6页浏览型号ICS9DB202CK-01LF的Datasheet PDF文件第7页 
PCI EXPRESS JITTER ATTENUATOR  
ICS9DB202-01  
GENERAL DESCRIPTION  
FEATURES  
One 0.7V current mode differential HCSL output pair  
The ICS9DB202-01 is a high performance 1-to-1  
ICS  
HiPerClockS™  
Differential-to HCSL Jitter Attenuator designed for  
One differential clock input  
use in PCI Express™ systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
bandwidth, high phase noise PLL frequency synthesizer. In these  
systems, a jitter attenuating device may be necessary in order to  
reduce high frequency random and deterministic jitter com-  
ponents from the PLL synthesizer and from the system board.  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Maximum output frequency: 140MHz  
Input frequency range: 90MHz - 140MHz  
VCO range: 450MHz - 700MHz  
Cycle-to-cycle jitter: 30ps (maximum)  
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):  
2.31ps (typical)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Current  
Set  
IREF  
-
+
32 31 30 29 28 27 26 25  
IREF  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
nc  
nc  
nc  
nc  
VDD  
nc  
nc  
nc  
VDDA  
CLK  
nCLK  
nc  
ICS9DB202-01  
nCLK  
CLK  
PCIEXT0  
Loop  
Filter  
Phase  
Detector  
VCO  
nc  
nPCIEXC0  
nc  
9
10 11 12 13 14 15 16  
Internal Feedback  
32-Lead VFQFN  
5mm x 5mm x 0.925 package body  
K Package  
Top View  
IDT/ ICSPCI EXPRESS JITTER ATTENUATOR  
1
ICS9DB202CK-01 REV. B FEBRUARY 18, 2009  

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