ICS9DB202CGT

更新时间： 2024-11-23 04:44:23

品牌	Logo	应用领域
艾迪悌 - IDT		衰减器 PC
页数	文件大小	规格书
13页	673K
描述
PCI EXPRESS JITTER ATTENUATOR

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中文翻译

获取价格

数据手册

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ICS9DB202CGT 数据手册

PCI EXPRESS JITTER ATTENUATOR

ICS9DB202

GENERAL DESCRIPTION

FEATURES

The ICS9DB202 is a high perfromance 1-to-2

Differential-to-HCSL Jitter Attenuator designed for

use in PCI Express™ systems. In some PCI

Express™ systems, such as those found in desktop

PCs, the PCI Express™ clocks are generated from

• Two 0.7V current mode differential HCSL output pairs

ICS

HiPerClockS™

• One differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

a low bandwidth, high phase noise PLL frequency synthesizer.

In these systems, a jitter-attenuating device may be necessary

in order to reduce high frequency random and deterministic

jitter components from the PLL synthesizer and from the system

board. The ICS9DB202 has two PLL bandwidth modes. In low

bandwidth mode, the PLL loop bandwidth is 500kHz.This setting

offers the best jitter attenuation and is still high enough to pass

a triangular input spread spectrum profile. In high bandwidth

mode, the PLL bandwidth is at 1MHz and allows the PLL to

pass more spread spectrum modulation.

• Maximum output frequency: 140MHz

• Input frequency range: 90MHz - 140MHz

• VCO range: 450MHz - 700MHz

• Output skew: 110ps (maximum)

• Cycle-to-cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

For serdes which have x10 reference multipliers instead of x12.5

multipliers, each of the two PCI Express™ outputs (PCIEX0:1)

can be set for 125MHz instead of 100MHz by configuring the

appropriate frequency select pins (FS0:1).

• 0°C to 70°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

packages

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

IREF

Current

Set

V^DDA

PLL_BW

CLK

BYPASS

IREF

FS1

V^DD

GND

PCIEXT1

PCIEXC1

V^DD

nCLK

FS0

V^DD

1 HiZ

0 Enabled

nOE0

GND

PCIEXT0

PCIEXC0

V^DD

PCIEXT0

nPCIEXC0

nCLK

CLK

Loop

Filter

Phase

Detector

0 ÷4

1 ÷5

nOE1

nOE0

VCO

ICS9DB202

20-Lead TSSOP

6.50mm x 4.40mm x 0.92

package body

FS0

÷5

G Package

Top View

Internal Feedback

PCIEXT1

nPCIEXC1

0 ÷5

1 ÷4

ICS9DB202

20-Lead, 209-MIL SSOP

5.30mm x 7.20mm x 1.75mm

body package

F Package

Top View

FS1

BYPASS

nOE1

1 HiZ

0 Enabled

IDT^™/ ICS^™PCI EXPRESS JITTER ATTENUATOR

ICS9DB202CG REV B JULY 14, 2006

12 3 4 5 6 7...13

中文翻译

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与ICS9DB202CGT相关器件

型号	品牌	获取价格	描述	数据表
ICS9DB202CK-01	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01LF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01LFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB202CK-01T	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 1 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95
ICS9DB206CFLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X
ICS9DB206CFLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X
ICS9DB206CLLF	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X
ICS9DB206CLLFT	IDT	获取价格	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X
ICS9DB206FT	IDT	获取价格	Clock Driver
ICS9DB206GT	IDT	获取价格	Clock Driver

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