ICS932S200
Integrated
Circuit
Systems, Inc.
Frequency Timing Generator for Dual Server/Workstation Systems
General Description
Features
•
Generates the following system clocks:
- 6 CPU clocks ( 2.5V, 100/133MHz)
- 6 PCI clocks, including 1 free running(3.3V,
33MHz)
The ICS932S200 is a dual CPU clock generator for
serverworks HE-T, HE-SL-T, LE-T chipsets for P III type
processors in a Dual-CPU system. Single ended CPU
clocks provide faster than 1.5V/ns transition times by
parallel connection of 2 CPU pins to each processor.
- 3 IOAPIC clocks (2.5V, 16.67MHz)
- 2 Fixed frequency 66MHz clocks(3.3V, 66MHz)
- 2 REF clocks(3.3V, 14.318MHz)
- 1 USB clock (3.3V, 48MHz)
Spread Spectrum may be enabled by driving the
SPREAD# pin active. Spread spectrum typically
reduces system EMI by 8dB to 10dB. This simplifies
EMI qualification without resorting to board design
iterations or costly shielding.The ICS932S200 employs
a proprietary closed loop design, which tightly controls
the percentage of spreading over process and
temperaturevariations.
•
•
•
Efficient power management through PD#,
CPU_STOP#andPCI_STOP#.
0.5% typical down spread modulation on CPU, PCI,
IOAPIC and 3V66 output clocks.
Uses external 14.318MHz crystal.
Key Specification:
•
•
•
•
•
•
•
•
•
•
CPU Output Jitter: 150ps
IOAPIC Output Jitter: 250ps
3V66, PCI Output Jitter: 250ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
Pin Configuration
3V66 Output Skew <250ps
GND
REF0
REF1
VDD
X1
X2
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
IOAPIC2
IOAPIC1
IOAPIC0
GND
IOAPIC Output Skew <250ps
CPU to 3V66 Output Offset: 0 - 1.5ns (CPU leads)
CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)
CPU to APIC Output Offset: 1.5 - 4.0ns (CPU
leads)
VDDL
CPUCLK5
CPUCLK4
GND
PCICLK_F
VDD
PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDD
VDDL
CPUCLK3
CPUCLK2
GND
Block Diagram
VDDL
CPUCLK1
CPUCLK0
GND
VDD
GND
PCI_STOP#
CPU_STOP#
PD#
SPREAD#
SEL1
PLL2
48MHz
VDD
PCICLK4
GND
X1
X2
XTAL
OSC
REF (1:0)
GND
GND
VDD
VDD
2
PLL1
Spread
CPU
DIVDER
CPUCLK (5:0)
6
GND
Spectrum
3V66_0
3V66_1
VDD
SEL0
VDD
48MHz
GND
IOAPIC
DIVDER
IOAPIC (2:0)
3
5
SEL 133/100#
PD#
PCI_STOP#
CPU_STOP#
SPREAD#
Control
Logic
PCI
DIVDER
Stop
PCICLK (4:0)
PCICLK_F
56-pin 300 mil SSOP
56-pin 240 mil TSSOP
SEL 133/100#
SEL0
3V66
DIVDER
3V66 (1:0)
Config.
Reg.
2
SEL1
0427C—07/03/02