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ICS932S202 PDF预览

ICS932S202

更新时间: 2024-09-07 21:53:47
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
14页 106K
描述
Frequency Timing Generator for Differential PIIIType Dual-CPU Systems

ICS932S202 数据手册

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ICS932S202  
Integrated  
Circuit  
Systems, Inc.  
Frequency Timing Generator for Differential PIII Type  
Dual-CPU Systems  
RecommendedApplication:  
KeySpecifications:  
Serverwork HE-T, HE-SL & LE-T Chipsets  
CPU Output Jitter: <150ps  
IOAPIC Output Jitter: <500ps  
48MHz, 3V66, PCI Output Jitter: <500ps  
Ref Output Jitter. <1000ps  
OutputFeatures:  
2 - CPUs @ 2.5V, up to 180MHz  
2 - CPU chipset @ 2.5V, up to 180MHz  
3 - IOAPIC @ 2.5V  
CPU Output Skew: <175ps  
IOAPIC Output Skew <250ps  
PCI Output Skew: <500ps  
3 - 3V66MHz @ 3.3V  
11 - PCIs @ 3.3V  
1 - 48MHz, @ 3.3V fixed  
3V66 Output Skew <250ps  
1 - 24/48MHz, @ 3.3V  
2 - REF @ 3.3V  
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =  
1.3ns)  
Features:  
CPU to PCI Output Offset: 0.0 - 1.5ns (typ =  
0.9ns)  
Up to 180MHz frequency support  
Support power management:Power down Mode  
from I2C programming.  
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =  
2.0ns)  
Spread spectrum for EMI control  
± 0.25% center spread).  
Uses external 14.318MHz crystal  
5 - FS pins for frequency select  
Block Diagram  
Pin Configuration  
GNDREF  
REF0  
*SEL24_48#/REF1  
VDDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDLAPIC  
IOAPIC0  
IOAPIC1  
GNDLAPIC  
IOAPIC2  
VDDLCPU  
CPUCLK0  
GNDLCPU  
CPUCLK1  
VDDLCPU  
CPU_CSCLK0  
CPU_CSCLK1  
GNDLCPU  
VDD66  
3V66_0  
3V66_1  
3V66_2  
GND66  
SDATA  
SCLK  
VDD48  
PLL2  
48MHz  
24_48MHz  
/ 2  
X2  
GNDPCI  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
*FS0/PCICLK0  
*FS1/PCICLK1  
VDDPCI  
*FS2/PCICLK2  
*FS3/PCICLK3  
GNDPCI  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
CPUCLK (1:0)  
CPU_CSCLK (1:0)  
PCICLK4  
PCICLK5  
VDDPCI  
PCICLK6  
PCICLK7  
GNDPCI  
PCICLK8  
PCICLK9  
PCICLK10  
VDDPCI  
IOAPIC  
DIVDER  
IOAPIC (2:0)  
SEL24_48#  
Control  
Logic  
PCI  
DIVDER  
PCICLK (10:0)  
SDATA  
SCLK  
FS (4:0)  
PD#  
Config.  
Reg.  
48MHz/FS4*  
24_48MHz  
GND48  
3V66  
DIVDER  
3V66 (2:0)  
PD#  
48-pin SSOP  
*120Kohmpull-uptoVDDonindicatedinputs.  
0600A—08/04/03  

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