Datasheet > ICS87016AY

ICS87016AY

更新时间： 2024-09-26 21:06:43

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
15页	139K
描述
Low Skew Clock Driver, 87016 Series, 16 True Output(s), 0 Inverted Output(s), CMOS, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

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ICS87016AY 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.19	系列：	87016
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	16	最高工作温度：	85 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	QCCN
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.8/3.3,3.3 V	传播延迟（tpd）：	4.5 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.17 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7 mm
最小 fmax：	250 MHz	Base Number Matches：	1

ICS87016AY 数据手册

PRELIMINARY

ICS87016

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-16

D^IFFERENTIAL-TO-LVCMOS CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS87016 is a low skew 1:16 clock generator • 16 LVCMOS outputs (4 banks of 4 outputs)

and is a member of the HiPerClockS family of High

Performance Clock Solutions. The device has 4

banks of 4 outputs and each bank can be inde-

pendently selected for ÷1 or ÷2 frequency opera-

• Selectable differential CLK1, nCLK1 or LVCMOS clock input

HiPerClockS™

• CLK1, nCLK1 pair can accept the following differential input

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

tion. Each bank also has its own power supply pins so that

the banks can operate at the following different voltage levels:

3.3V, 2.5V, and 1.8V. The low impedance LVCMOS outputs

are designed to drive 50Ω series or parallel terminated

transmission lines.

• CLK0 supports the following input types: LVCMOS, LVTTL

• Maximum output frequency: 250MHz

• Independent bank control for ÷1 or ÷2 operation

• Independent bank voltage settings for 3.3V, 2.5V, or

1.8V operation

The divide select inputs, DIV_SELA:DIV_SELD, control the

output frequency of each bank. The output banks can be

independently selected for ÷1 or ÷2 operation. The bank enable

inputs, CLK_ENA:CLK_END, support enabling and disabling

each bank of outputs individually. The CLK_ENA:CLK_END

circuitry has a synchronizer to prevent runt pulses when

enabling or disabling the clock outputs. The master reset

input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the

active and high impedance states of all outputs. This pin has

an internal pull-up resistor and is normally used only for test

purposes or in systems which use low power modes.

• Asynchronous clock enable/disable

• Output skew: 144ps (typical)

• Bank skew: 32ps (typical)

• Part-to-part skew: TBD

• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

The ICS87016 is characterized to operate with the core at 3.3V

and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output,

and part-to-part skew characteristics make the 87016 ideal for

those clock applications demanding well-defined performance

and repeatability.

BLOCK DIAGRAM

nMR/OE

PIN ASSIGNMENT

CLK0

÷1

÷2

QA0 - QA3

48 47 46 45 44 43 42 41 40 39 38 37

V^DD

CLK0

GND

QB0

CLK1

nCLK1

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

CLK_ENA

CLK_ENB

CLK_ENC

CLK_END

nMR/OE

V^DDOB

QB1

QB0 - QB3

QC0 - QC3

CLK_SEL

GND

QB2

DIV_SELA

DIV_SELB

ICS87016

V^DDOB

QB3

GND

QC0

V^DDOC

QC1

DIV_SELC

DIV_SELD

QD0 - QD3

GND

13 14 15 16 17 18 19 20 21 22 23 24

CLK_ENA

CLK_ENB

CLK_ENC

CLK_END

48-Pin LQFP

7mm x 7mm x 1.4mm

YPackage

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

87016AY

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 6, 2002

12 3 4 5 6 7...15

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与ICS87016AY相关器件

型号	品牌	获取价格	描述	数据表
ICS8701AY-01	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.
ICS8701AY-01LF	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AY-01LFT	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AY-01T	IDT	获取价格	Low Skew Clock Driver, 15 True Output(s), 5 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.
ICS8701AYI-01	IDT	获取价格	Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AYI-01LF	IDT	获取价格	Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AYI-01LFT	IDT	获取价格	Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701AYI-01T	IDT	获取价格	Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8701CY	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8701CYI	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR

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