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ICS855011AG PDF预览

ICS855011AG

更新时间: 2024-11-11 20:00:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 215K
描述
Low Skew Clock Driver, 855011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 MM X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8

ICS855011AG 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:8
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.49系列:855011
输入调节:DIFFERENTIALJESD-30 代码:S-PDSO-G8
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3 mm
Base Number Matches:1

ICS855011AG 数据手册

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PRELIMINARY  
ICS855011  
LOW SKEW, 1-TO-2  
DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS855011 is a low skew, high perfor- Two differential 2.5V/3.3V CML outputs  
ICS  
mance 1-to-2 Differential-to-2.5V/3.3V CML  
One differential PCLK, nPCLK input pair  
HiPerClockS™  
Fanout Buffer and a member of the  
HiPerClockS™ family of High Performance  
Clock Solutions from IDT. The ICS855011  
PCLK, nPCLK pair can accept the following  
differential input levels: LVPECL, LVDS, CML, SSTL  
is characterized to operate from either a 2.5V or a  
3.3V power supply. Guaranteed output and part-to-  
part skew characteristics make the ICS855011 ideal  
for those clock distribution applications demanding  
well defined performance and repeatability.  
Output frequency: >3GHz  
Translates any single ended input signal to 3.3V  
LVPECL levels with resistor bias on nPCLK input  
Output skew: 5ps (typical)  
Part-to-part skew: TBD  
Propagation delay: 242ps (typical)  
Operating voltage supply range:  
VCC = 2.375V to 3.8V, VEE = 0V  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
Q1  
Vcc  
1
2
3
4
8
7
6
5
Q0  
nQ0  
PCLK  
nPCLK  
VEE  
PCLK  
nPCLK  
Q1  
nQ1  
nQ1  
ICS855011  
8-LeadTSSOP  
3mm x 3mm x 0.95mm package body  
G Package  
Top View  
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product  
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-  
tions without notice.  
855011AG  
1
REV. A JANUARY 16, 2008  

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