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ICS43002A41 PDF预览

ICS43002A41

更新时间: 2024-11-14 04:22:55
品牌 Logo 应用领域
艾迪悌 - IDT 石英晶振压控振荡器衰减器
页数 文件大小 规格书
23页 1534K
描述
700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

ICS43002A41 数据手册

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TM  
700MHZ, FEMTOCLOCK VCXO BASED  
ICS843002I-41  
SONET/SDH JITTER ATTENUATOR  
General Description  
Features  
The ICS843002I-41 is a member of the  
Two Differential LVPECL outputs  
S
IC  
HiperClockS™ family of high performance clock  
solutions from IDT. The ICS843002I-41 is a PLL  
based synchronous clock generator that is  
Selectable CLKx, nCLKx differential input pairs  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or  
single-ended LVCMOS or LVTTL levels  
optimized for SONET/SDH line card applications  
where jitter attenuation and frequency translation is needed. The  
device contains two internal PLL stages that are cascaded in  
series. The first PLL stage uses a VCXO which is optimized to  
provide reference clock jitter attenuation and to be jitter tolerant,  
and to provide a stable reference clock for the 2nd PLL stage  
(typically 19.44MHz). The second PLL stage provides additional  
frequency multiplication (x32), and it maintains low output jitter by  
using a low phase noise FemtoClock™VCO. PLL multiplication  
ratios are selected from internal lookup tables using device input  
selection pins. The device performance and the PLL multiplication  
ratios are optimized to support non-FEC (non-Forward Error  
Correction) SONET/SDH applications with rates up to OC-48  
(SONET) or STM-16 (SDH). The VCXO requires the use of an  
external, inexpensive pullable crystal. VCXO PLL uses external  
passive loop filter components which are used to optimize the PLL  
loop bandwidth and damping characteristics for the given  
line card application.  
Maximum output frequency: 700MHz  
FemtoClock VCO frequency range: 560MHz - 700MHz  
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal  
(12kHz to 20MHz): 0.81ps (typical)  
Full 3.3V or mixed 3.3V core/2.5V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
The ICS843002I-41 includes two clock input ports. Each one can  
accept either a single-ended or differential input. Each input port  
also includes an activity detector circuit, which reports input clock  
activity through the LOR0 and LOR1 logic output pins. The two  
input ports feed an input selection mux. “Hitless switching” is  
accomplished through proper filter tuning. Jitter transfer and  
wander characteristics are influenced by loop filter tuning, and  
phase transient performance is influenced by both loop filter  
tuning and alignment error between the two reference clocks.  
32 31 30 29 28 27 26 25  
1
2
3
24  
23  
22  
LF1  
LF0  
LOR0  
LOR1  
nc  
ISET  
Typical ICS843002I-41 configuration in SONET/SDH Systems:  
VCXO 19.44MHz crystal  
VCC  
VCCO_LVCMOS  
VCCO_LVPECL  
nQB  
4
5
21  
20  
CLK0  
nCLK0  
CLK_SEL  
QA_SEL2  
6
7
8
19  
18  
17  
QB  
Loop bandwidth: 50Hz - 250Hz  
VEE  
Input Reference clock frequency selections:  
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,  
622.08MHz  
9
10 11 12 13 14 15 16  
Output clock frequency selections:  
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,  
Hi-Z  
ICS843002I-41  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR  
1
ICS843002AKI-41 REV. A OCTOBER 25, 2007  

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