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ICS43004AI04L PDF预览

ICS43004AI04L

更新时间: 2024-11-14 11:14:27
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
14页 184K
描述
FEMTOCLOCKS-TM CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER

ICS43004AI04L 数据手册

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ICS843004I-04  
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-  
3.3V LVPECL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS843004I-04 is a 4 output LVPECL • Four LVPECL outputs  
ICS  
HiPerClockS™  
Synthesizer optimized to generate clock  
frequencies for a variety of high performance  
• Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
applications and is  
a member of the  
HiPerClocksTM family of high performance  
• Supports the following applications: SONET/SDH, SATA,  
or 10Gb Ethernet  
clock solutions from ICS. This device can select its input  
reference clock from either a crystal input or a single-  
ended clock signal. It can be configured to generate 4  
outputs with individually selectable divide-by-one or  
divide-by-four function via the 4 frequency select pins  
(F_SEL[3:0]). The ICS843004I-04 uses ICS’ 3rd  
generation low phase noise VCO technology and can  
achieve 1ps or lower typical rms phase jitter. This  
ensures that it will easily meet clocking requirements  
for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/  
OC12/OC-48). This device is suitable for multi-rate and  
multiple port line card applications. The ICS843004I-04  
is conveniently packaged in a small 24-pin TSSOP  
package.  
• Output frequency range: 140MHz - 170MHz,  
560MHz - 680MHz  
• VCO range: 560MHz - 680MHz  
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz  
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz  
crystal (12kHz - 20MHz): 0.82ps (typical)  
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz  
crystal (1.875MHz - 20MHz): 0.57ps (typical)  
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz  
crystal (12kHz - 20MHz): 0.94ps (typical)  
• Full 3.3V supply mode  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and lead-free RoHS compliant  
packages  
PIN ASSIGNMENT  
BLOCK DIAGRAM  
XTAL_IN  
nQ1  
Q1  
VCCo  
Q0  
1
2
3
4
5
6
7
8
24  
23  
22  
nQ2  
Q2  
VCCO  
Q3  
OSC  
0
÷1  
÷4  
0
1
Q0  
XTAL_OUT  
CLK  
nQ0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Phase  
Detector  
VCO  
Pulldown  
nQ0  
MR  
F_SEL3  
nc  
nQ3  
VEE  
F_SEL2  
INPUT_SEL  
CLK  
1
Pulldown  
INPUT_SEL  
M = ÷32  
9
VCCA  
Pulldown  
Pullup  
10  
11  
12  
F_SEL0  
VCC  
VEE  
XTAL_IN  
MR  
Q1  
0
1
F_SEL0  
F_SEL1  
XTAL_OUT  
nQ1  
Pullup  
Pullup  
Pullup  
ICS843004I-04  
24-Lead TSSOP  
4.40mm x 7.8mm x 0.92mm  
package body  
F_SEL1  
Q2  
0
1
nQ2  
G Package  
Top View  
F_SEL2  
Q3  
0
1
nQ3  
F_SEL3  
843004AGI-04  
www.icst.com/products/hiperclocks.html  
REV.A FEBRUARY 15, 2006  
1

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