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IC42S16102-5BG PDF预览

IC42S16102-5BG

更新时间: 2024-02-27 23:07:49
品牌 Logo 应用领域
矽成 - ICSI 内存集成电路动态存储器时钟
页数 文件大小 规格书
78页 764K
描述
512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102-5BG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, TSOP50,.46,32Reach Compliance Code:compliant
风险等级:5.75访问模式:DUAL BANK PAGE BURST
最长访问时间:4.5 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G50
JESD-609代码:e3内存密度:16777216 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:50字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSOP50,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.15 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

IC42S16102-5BG 数据手册

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IC42S16102  
512K x 16 Bits x 2 Banks (16-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
FEATURES  
DESCRIPTION  
ICSI's 16Mb Synchronous DRAM IC42S16102 is organized  
as a 524,288-word x 16-bit x 2-bank for improved  
performance. The synchronous DRAMs achieve high-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
• Driver Strength for High capacitive bus loading  
• Clock frequency: 200, 166, 143 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Two banks can be operated simultaneously and  
independently  
• Dual internal bank controlled by A11 (bank select)  
• Single 3.3V power supply  
PIN CONFIGURATIONS  
50-Pin TSOP-2  
VCC  
DQ0  
DQ1  
GNDQ  
DQ2  
DQ3  
VCCQ  
DQ4  
DQ5  
GNDQ  
DQ6  
DQ7  
VCCQ  
LDQM  
WE  
1
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
GND  
DQ15  
DQ14  
GNDQ  
DQ13  
DQ12  
VCCQ  
DQ11  
DQ10  
GNDQ  
DQ9  
DQ8  
VCCQ  
NC  
• LVTTL interface  
2
• Programmable burst length  
3
4
– (1, 2, 4, 8, full page)  
5
• Programmable burst sequence:  
Sequential/Interleave  
• Auto refresh, self refresh  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
• 4096 refresh cycles every 64 ms  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
• Burst read/write and burst read/single write  
UDQM  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
operations capability  
• Burst termination by burst stop and precharge  
command  
• Byte controlled by LDQM and UDQM  
A11  
A9  
A10  
A8  
A0  
A7  
A1  
A6  
• Package 400mil 50-pin TSOP-2 and 60ball(16M)  
A2  
A5  
VF-BGA  
A3  
A4  
VCC  
GND  
• Pb(lead)-free package is available  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
2
Integrated Circuit Solution Inc.  
DR042-0A 01/18/2005  

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