Datasheet > IBM13N8644HCB-260T

IBM13N8644HCB-260T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
19页	341K
描述
x64 SDRAM Module

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IBM13N8644HCC

IBM13N8734HCC

8M x 64/72 One-Bank Unbuffered SDRAM Module

Features

• 168-Pin Unbuffered 8-Byte Dual In-Line Memory

Module

• Programmable Operation:

- CAS Latency: 2, 3

• 8Mx64/72 Synchronous DRAM DIMM

• Three speed sorts:

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page

(Full-Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• -260 and -360 for PC100 applications

• -10 for 66MHz applications (typical)

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• Suspend Mode and Power Down Mode

• 12/9/2 Addressing (Row/Column/Bank)

• 4096 Refresh cycles distributed across 64ms

• Serial Presence Detect

• SDRAMs have 4 internal banks

• Module has 1 bank

• Fully Synchronous to positive Clock Edge

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

• Card size: 5.25" x 1.375" x 0.106"

• Gold contacts

• SDRAMs in TSOP Type II Package

Description

IBM13N8644HCC / IBM13N8734HCC are unbuf-

fered 168-pin Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as

8Mx64 and 8Mx72 high-speed memory arrays. The

DIMMs use eight (8Mx64) or nine (8Mx72) 8Mx8

SDRAMs in 400mil TSOP II packages. The DIMMs

achieve high-speed data transfer rates of up to

100MHz by employing a prefetch/pipeline hybrid

architecture that supports the JEDEC 1N rule while

allowing very low burst power.

ating modes are defined by combinations of RAS,

CAS, WE, S0/S2, DQMB, and CKE0 signals. A

command decoder initiates the necessary timings

for each operation. A 14-bit address bus accepts

address information in a row/column multiplexing

arrangement.

Prior to any Access operation, the CAS latency,

burst type, burst length, and Burst operation type

must be programmed into the DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The -10 speed sort DIMMs comply with JEDEC

standards for 168-pin unbuffered SDRAM DIMMs.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

The -260 and -360 speed sort DIMMs are compati-

ble with the Intel PC100 SDRAM unbuffered DIMM

specification.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint. Related products include both EDO DRAM

and SDRAM unbuffered DIMMs in both non-parity

x64 and ECC-Optimized x72 configurations.

All inputs are sampled at the positive edge of each

externally supplied clock (CK0, CK2). Internal oper-

Card Outline

(Front)

(Back)

10 11

94 95

168

40 41

124 125

19L7295.E93875B

12/99

Use is further subject to the provisions at the end of this document.

Page 1 of 19

12 3 4 5 6 7...19

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与IBM13N8644HCB-260T相关器件

型号	品牌	获取价格	描述	数据表
IBM13N8644HCB-360T	ETC	获取价格	x64 SDRAM Module
IBM13N8644HCB-75AT	ETC	获取价格	x64 SDRAM Module
IBM13N8644HCC-10T	IBM	获取价格	Synchronous DRAM Module, 8MX64, 9ns, CMOS, DIMM-168
IBM13N8644HCC-260T	IBM	获取价格	Synchronous DRAM Module, 8MX64, 6ns, CMOS, DIMM-168
IBM13N8644HCC-360T	IBM	获取价格	Synchronous DRAM Module, 8MX64, 6ns, CMOS, DIMM-168
IBM13N8734HCB-260T	ETC	获取价格	x72 SDRAM Module
IBM13N8734HCB-360T	ETC	获取价格	x72 SDRAM Module
IBM13N8734HCB-75AT	ETC	获取价格	x72 SDRAM Module
IBM13N8734HCC-10T	ETC	获取价格	x72 SDRAM Module
IBM13N8734HCC-260T	IBM	获取价格	Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-168

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