Datasheet > IBM0316169CT3-13

IBM0316169CT3-13

更新时间： 2024-11-11 19:37:39

品牌	Logo	应用领域
国际商业机器公司 - IBM		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
100页	1216K
描述
Synchronous DRAM, 1MX16, 12ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

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技术参数
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IBM0316169CT3-13 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP50,.46,32
针数：	50	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.71	Is Samacsys：	N
访问模式：	DUAL BANK PAGE BURST	最长访问时间：	12 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	76 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G50	JESD-609代码：	e0
长度：	20.95 mm	内存密度：	16777216 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	50	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装等效代码：	TSOP50,.46,32	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	4096	座面最大高度：	1.2 mm
自我刷新：	YES	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.002 A	子类别：	DRAMs
最大压摆率：	0.155 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm	Base Number Matches：	1

IBM0316169CT3-13 数据手册

IBM0316409C 4M

x 412/10, 3.3V, SR. IBM0316169C 1M x 1612/8, 3.3V, SR. IBM0316809C 2M x 812/9, 3.3V, SR.

IBM0316409C IBM0316809C

IBM0316169C

16Mbit Synchronous DRAM

Features

• High Performance:

CAS latency = 3

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4,x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 refresh cycles/64ms

-10 -11 -12 -13 Units

f_CK

t_CK3

t_AC3

Clock Frequency

Clock Cycle

100 91

MHz

Clock Access Time

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Dual Banks controlled by A11 (Bank Select)

• Programmable CAS Latency: 1,2,3

• Random Column Address every CLK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• Programmable Burst Length: 1,2,4,8,full-page

• LVTTL compatible

• Programmable Wrap Sequence: Sequential or

Interleave

• Package: 40 pin 400 mil TSOP-Type II (x4,x8)

50 pin 400 mil TSOP-Type II (x16)

Description

The

IBM0316409C,

IBM0316809C,

and

addresses (A0-A10) and a bank select address

(A11) are strobed with RAS. Ten column addresses

(A0-A9) plus a bank select address (A11) are

strobed with CAS. Column address A9 is dropped

on the x8 device and column addresses A8 and A9

are dropped on the x16 device.

IBM0316169C are dual bank Synchronous DRAM’s

organized as 2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x

2 Bank, and 512Kbit x 16 I/O x 2 Bank, respectively.

These synchronous devices achieve high speed

data transfer rates of up to 100MHz by employing a

chip architecture that prefetches multiple bits and

then synchronizes the output data to a system clock.

The chip is fabricated with IBM’s advanced 16Mbit

single transistor CMOS DRAM process technology.

The device is designed to comply with all

JEDEC standards set for synchronous DRAM prod-

ucts, both electrically and mechanically. All of the

control, address and data input/output circuits are

synchronized with the positive edge of an externally

supplied clock.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A9

during a mode register set cycle. In addition, it is

possible to program a multiple burst sequence with

single write cycle for write through cache operation.

Operating the two memory banks in an inter-

leave fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

100MHz is possible depending on burst length, CAS

latency, and speed grade of the device.

RAS, CAS, WE, and CS are pulsed signals

which are examined at the positive edge of each

externally applied clock (CLK). Internal chip operat-

ing modes are defined by combinations of these sig-

Auto Refresh (CBR) and Self Refresh operation

are supported. These devices operate with a single

3.3V ± 0.3V power supply and are available in

400mil TSOP Type II packages.

nals and

command decoder initiates the

necessary timings for each operation. A twelve bit

address bus accepts address data in the conven-

tional RAS/CAS multiplexing style. Eleven row

Use is further subject to the provisions at the end of this document.

07H3997

SA14-4711-02

Revised 05/96

Page 1 of 100

12 3 4 5 6 7...100

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与IBM0316169CT3-13相关器件

型号	品牌	获取价格	描述	数据表
IBM0316169CT3-80	IBM	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50
IBM0316169CT3D-10	IBM	获取价格	Synchronous DRAM, 1MX16, 8ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50
IBM0316169QT3-70	IBM	获取价格	Synchronous DRAM, 1MX16, 5ns, CMOS, PDSO50
IBM0316409CT3-10	IBM	获取价格	Synchronous DRAM, 4MX4, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
IBM0316409CT3-10H	ETC	获取价格	x4 SDRAM
IBM0316409CT3-11	ETC	获取价格	x4 SDRAM
IBM0316409CT3-12H	IBM	获取价格	Synchronous DRAM, 4MX4, 9ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
IBM0316409CT3-13	IBM	获取价格	Synchronous DRAM, 4MX4, 12ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
IBM0316409CT3E-80	IBM	获取价格	Synchronous DRAM, 4MX4, 6ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
IBM0316409DT3-70	IBM	获取价格	Synchronous DRAM, 4MX4, 5ns, CMOS, PDSO44

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