5秒后页面跳转
捷配首页

Datasheet > IBM0316809CT3D-360
IBM0316809CT3D-360 PDF预览

IBM0316809CT3D-360

更新时间： 2024-01-11 15:33:21
品牌 Logo 应用领域
国际商业机器公司 - IBM 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
120页 1896K
描述
Synchronous DRAM, 2MX8, 5.5ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44

阅读下载

获取价格

IBM0316809CT3D-360 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSOP44,.46,32
针数：44Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.92Is Samacsys：N
访问模式：DUAL BANK PAGE BURST最长访问时间：5.5 ns
其他特性：AUTO/SELF REFRESH最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMON交错的突发长度：1,2,4,8
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
长度：18.41 mm内存密度：16777216 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：8
功能数量：1端口数量：1
端子数量：44字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
刷新周期：4096座面最大高度：1.2 mm
自我刷新：YES连续突发长度：1,2,4,8,FP
最大待机电流：0.002 A子类别：DRAMs
最大压摆率：0.175 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.16 mmBase Number Matches：1

IBM0316809CT3D-360 数据手册

 浏览型号IBM0316809CT3D-360的Datasheet PDF文件第2页浏览型号IBM0316809CT3D-360的Datasheet PDF文件第3页浏览型号IBM0316809CT3D-360的Datasheet PDF文件第4页浏览型号IBM0316809CT3D-360的Datasheet PDF文件第5页浏览型号IBM0316809CT3D-360的Datasheet PDF文件第6页浏览型号IBM0316809CT3D-360的Datasheet PDF文件第7页 
Discontinued (12/98 - last order; 9/99 last ship)  
.
IBM0316409C IBM0316809C IBM0316169C  
IBM03164B9C  
16Mb Synchronous DRAM-Die Revision D  
Features  
• Multiple Burst Read with Single Write Option  
• Automatic and Controlled Precharge Command  
• Data Mask for Read/Write control (x4, x8)  
• Dual Data Mask for byte control (x16)  
• Auto Refresh (CBR), Self Refresh (SR)  
• Suspend Mode and Power Down Mode  
• 4096 refresh cycles/64ms  
• High Performance:  
-80  
CL=3  
-360  
CL=3  
-10  
CL=3  
Units  
fCK  
tCK  
tAC  
Clock Frequency  
Clock Cycle  
125  
8
100  
10  
100 MHz  
10  
8
ns  
ns  
Clock Access Time  
6
5.5  
• Single Pulsed RAS Interface  
• Fully Synchronous to Positive Clock Edge  
• Random Column Address every CLK (1-N Rule)  
• Single 3.3V ± 0.3V Power Supply  
• Dual Banks controlled by A11 (Bank Select)  
• Programmable CAS Latency: 1,2,3  
• Supports LVTTL I/O interface  
• Programmable Burst Length: 1,2,4,8,full-page  
• Package: 44 pin 400 mil TSOP-Type II (x4,x8)  
50 pin 400 mil TSOP-Type II (x16)  
2-High Stack TSOJ  
• Programmable Wrap Sequence: Sequential or  
Interleave  
Description  
IBM’s 0316409C, 0316809C, and 0316169C  
are dual bank Synchronous DRAMs organized as  
2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x 2 Bank, and  
512Kbit x 16 I/O x 2 Bank, respectively. These  
address A9 is dropped on the x8 device and column  
addresses A8 and A9 are dropped on the x16  
device. Access to the lower or upper DRAM in a  
stacked device is controlled by CS0 and CS1.  
devices support LVTTL I/O interface levels.  
stacked version of the x 4 component is also  
offered. These synchronous devices achieve high  
speed data transfer rates of up to 125 MHz. The  
chip is fabricated with IBM’s advanced 16Mbit  
CMOS DRAM process technology.  
A
Prior to any access operation, the CAS latency,  
burst length, and burst sequence must be pro-  
grammed into the device by address inputs A0-A11  
during a mode register set cycle. In addition, it is  
possible to program a multiple burst sequence with  
single write cycle for write through cache operation.  
Operating the two memory banks in an inter-  
leave fashion allows random access operation to  
occur at a higher rate than is possible with standard  
DRAMs. A sequential and gapless data rate of up to  
125 MHz is possible depending on burst length,  
CAS latency, and speed grade of the device.  
The device is designed to comply with all  
JEDEC standards set for synchronous DRAM prod-  
ucts, both electrically and mechanically. All of the  
control, address and data input/output circuits are  
synchronized with the positive edge of an externally  
supplied clock (CLK).  
Internal chip operating modes are defined by  
combinations of RAS, CAS, WE, and CS and a com-  
mand decoder initiates the necessary timings for  
each operation. A twelve bit address bus accepts  
address data in the conventional RAS/CAS multi-  
plexing style. Eleven row addresses (A0-A10) and a  
bank select address (A11) are strobed with RAS.  
Ten column addresses (A0-A9) plus A10 and a bank  
select address (A11) are strobed with CAS. Column  
Auto Refresh (CBR) and Self Refresh (SR)  
operation are supported. Refreshing both decks of a  
stacked device simultaneously is allowed during  
Self Refresh but all other stacked device operations  
must be performed on a single deck at a time.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
08J3348.E35853  
5/98  
 
1234567...120

下载PDF

与IBM0316809CT3D-360相关器件

型号 品牌 描述 获取价格 数据表
IBM0316809DT3-80 IBM Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44

获取价格
IBM03168B9DT3-80 IBM Synchronous DRAM Module, 2MX8, 6ns, CMOS, PDSO44

获取价格
IBM03168B9QT3-70 IBM Synchronous DRAM Module, 2MX8, 5ns, CMOS, PDSO44

获取价格
IBM03168B9QT3-80 IBM Synchronous DRAM Module, 2MX8, 6ns, CMOS, PDSO44

获取价格
IBM0317329NQ6A-10 ETC Synchronous Graphics RAM (SGRAM)

获取价格
IBM0317329NQ6A-7 ETC Synchronous Graphics RAM (SGRAM)

获取价格

与IBM0316809CT3D-360相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证