Datasheet > IBM0325404CT3A-10

IBM0325404CT3A-10

更新时间： 2024-01-04 03:23:25

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
68页	1014K
描述
x4 SDRAM

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IBM0325404CT3A-10 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP54,.46,32	针数：	54
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.56
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	9 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54	JESD-609代码：	e0
长度：	22.22 mm	内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	4
功能数量：	1	端口数量：	1
端子数量：	54	字数：	16777216 words
字数代码：	16000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16MX4	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装等效代码：	TSOP54,.46,32	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	8192	座面最大高度：	1.2 mm
自我刷新：	YES	连续突发长度：	1,2,4,8
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.09 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm	Base Number Matches：	1

IBM0325404CT3A-10 数据手册

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IBM0325404 IBM0325804

IBM0325164 IBM03254B4

EC Update (-10)

256Mb Synchronous DRAM - Die Revision A

Features

• High Performance:

• Programmable Burst Length: 1, 2, 4, or 8

• Programmable Wrap: Sequential or Interleave

-75A -260, -360, -10,

CL=3 CL=2 CL=3 CL=3

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge command

• Data Mask for Read/Write control (x4, x8) and

Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend mode and Power Down mode

• Standard Power operation

Units

Clock Frequency

133

7.5

—

100

—

100

—

100 MHz

Clock Cycle

Clock Access Time¹

Clock Access Time²

5.4

• 8192 Refresh cycles/64ms

Note: Terminated load, Unterminated load. See AC Characteristics (page 39).

• Random Column Address every CLK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Single-pulsed RAS interface

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BS0, BS1 (Bank

Selects)

• Packages:

- 54-pin 400 mil TSOP-Type II

- 66-pin 400 mil 2-High Stack TSOJ

• Programmable CAS Latency: 2, 3

Description

The IBM0325404, IBM0325804, and IBM0325164

are four bank Synchronous DRAMs organized as

16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and

4Mbit x 16 I/O x 4 Bank, respectively. IBM03254B4,

a stacked version of the x4 component, is also

offered. These synchronous devices achieve high-

speed data-transfer rates of up to 133 MHz by

employing a pipeline chip architecture that synchro-

nizes the output data to a system clock. The chip is

fabricated with IBM’s advanced 256Mbit single tran-

sistor CMOS DRAM process technology.

with CAS. Column address A11 is dropped on the

x8 device and column addresses A9 and A11 are

dropped on the x16 device. Access to the lower or

upper DRAM in a stacked device is controlled by

CS0 and CS1.

Prior to any access, the CAS latency, burst length,

and sequence must be programmed into the device

by address inputs A0-A12, BS0, BS1 during a Mode

Multiple Burst sequence with single write cycle for

write-through cache operation.

The device is designed to comply with all JEDEC

standards set for Synchronous DRAM products,

both electrically and mechanically. All the control,

address, and data input/output (I/O or DQ) circuits

are synchronized with the positive edge of an exter-

nally supplied clock.

Operating the four memory banks in an interleave

fashion allows random access operation to occur at

a higher rate than is possible with standard DRAMs.

A sequential and gapless data rate of up to 133 MHz

is possible depending on burst length, CAS latency,

and speed grade of the device. Simultaneous opera-

tion of both decks of a stacked device is allowed,

depending on the operation being done.

RAS, CAS, WE, and CS are pulsed signals which

are examined at the positive edge of each externally

applied clock (CLK). Internal chip operating modes

are defined by combinations of these signals, and a

command decoder initiates the necessary timings

for each operation. A fifteen-bit address bus accepts

address data in the conventional RAS/CAS multi-

plexing style. Thirteen row addresses (A0-A12) and

two bank select addresses (BS0, BS1) are strobed

with RAS. Eleven column addresses (A0-A9, A11)

plus bank select addresses and A10 are strobed

Auto Refresh (CBR), and Self Refresh operation are

supported.

29L0000.E36980A

7/99

Use is further subject to the provisions at the end of this document.

Page 1 of 68

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与IBM0325404CT3A-10相关器件

型号	品牌	获取价格	描述	数据表
IBM0325404CT3A-260	ETC	获取价格	x4 SDRAM
IBM0325404CT3A-360	ETC	获取价格	x4 SDRAM
IBM0325404CT3A-68	IBM	获取价格	Synchronous DRAM, 16MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
IBM0325404CT3A-75A	ETC	获取价格	x4 SDRAM
IBM03254B4CT3A-10	ETC	获取价格	x4 SDRAM Module
IBM03254B4CT3A-260	ETC	获取价格	x4 SDRAM Module
IBM03254B4CT3A-360	ETC	获取价格	x4 SDRAM Module
IBM03254B4CT3A-75A	ETC	获取价格	x4 SDRAM Module
IBM0325804CT3A-10	ETC	获取价格	x8 SDRAM
IBM0325804CT3A-260	ETC	获取价格	x8 SDRAM

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