Datasheet > IBM0364164CT3B-68

IBM0364164CT3B-68

更新时间： 2024-01-29 17:16:06

品牌	Logo	应用领域
国际商业机器公司 - IBM		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
72页	1201K
描述
Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

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IBM0364164CT3B-68 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP54,.46,32
针数：	54	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.91	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	6 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	147 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	R-PDSO-G54
JESD-609代码：	e0	长度：	22.22 mm
内存密度：	67108864 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX16
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.2 mm	自我刷新：	YES
连续突发长度：	1,2,4,8,FP	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.145 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10.16 mm
Base Number Matches：	1

IBM0364164CT3B-68 数据手册

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Discontinued (8/99 - last order; 12/99 - last ship)

IBM036440416M

x 412/10/2, 3.3V 72. IBM03644B432M x 412/10/2, 3.3V 72. IBM03641644M x 1612/8/2, 3.3V 72. IBM03648048M x 412/9/2, 3.3V 72.

IBM0364804 IBM0364164

IBM0364404 IBM03644B4

64Mb Synchronous DRAM - Die Revision B

Features

• Programmable Wrap: Sequential or Interleave

• High Performance:

• Multiple Burst Read with Single Write Option

-68, -260, -360, -10,

CL=3 CL=3 CL=3 CL=3

Units

• Automatic and Controlled Precharge Command

f_CK

t_CK

t_AC

Clock Frequency

Clock Cycle

147

6.8

135

7.4

—

135

7.4

—

100 MHz

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard or Low Power operation

• 4096 refresh cycles/64ms

Clock Access Time

—

1. Terminated load. See AC Characteristics on page 44.

2. Unterminated load. See AC Characteristics on page 44.

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Random Column Address every CLK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Four Banks controlled by A12/A13 (Bank

Select)

• Programmable CAS Latency: 2, 3

• Package: 54-pin 400 mil TSOP-Type II

2 High Stack TSOJ

• Programmable Burst Length: 1, 2, 4, 8, full-page

Description

The IBM0364404, IBM0364804, and IBM0364164

are four-bank Synchronous DRAMs organized as

4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and

1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,

a stacked version of the x4 component, is also

offered. These synchronous devices achieve high-

speed data transfer rates of up to 147MHz by

employing a pipeline chip architecture that synchro-

nizes the output data to a system clock. The chip is

fabricated with IBM’s advanced 64Mbit single tran-

sistor CMOS DRAM process technology.

and two bank select addresses (A12, A13) are

strobed with RAS. Ten column addresses (A0-A9)

plus bank select addresses and A10 are strobed

with CAS. Column address A9 is dropped on the x8

device and column addresses A8 and A9 are

dropped on the x16 device. Access to the lower or

upper DRAM in a stacked device is controlled by

CS0 and CS1, respectively.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A13

during a mode register set cycle. In addition, it is

possible to program a multiple burst sequence with

single write cycle for write through cache operation.

The device is designed to comply with all JEDEC

standards for synchronous DRAM products, both

electrically and mechanically. All the control,

address, and data input/output (I/O or DQ) circuits

are synchronized with the positive edge of an exter-

nally supplied clock.

Operating the four memory banks in an interleave

fashion allows random access operation to occur at

a higher rate than is possible with standard DRAMs.

A sequential and gapless data rate of up to 147MHz

is possible depending on burst length, CAS latency,

and speed grade of the device. Simultaneous oper-

ation of both decks of a stacked device is allowed,

depending on the operation being done.

RAS, CAS, WE, and CS are pulsed signals which

are examined at the positive edge of each externally

applied clock (CLK). Internal chip operating modes

are defined by combinations of these signals, and a

command decoder initiates the necessary timings

for each operation. A fourteen-bit address bus

accepts address data in the conventional RAS/CAS

multiplexing style. Twelve row addresses (A0-A11)

Auto Refresh (CBR), Self Refresh, and Low Power

operation are supported.

Use is further subject to the provisions at the end of this document.

19L3264.E35855A

1/28/99

Page 1 of 72

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与IBM0364164CT3B-68相关器件

型号	品牌	获取价格	描述	数据表
IBM0364164CT3C-10	ETC	获取价格	x16 SDRAM
IBM0364164CT3C-260	ETC	获取价格	x16 SDRAM
IBM0364164CT3C-360	ETC	获取价格	x16 SDRAM
IBM0364164CT3C-68	ETC	获取价格	x16 SDRAM
IBM0364164PT3B-10	IBM	获取价格	Synchronous DRAM, 4MX16, 9ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
IBM0364164PT3B-360	IBM	获取价格	Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
IBM0364164PT3C-10	ETC	获取价格	x16 SDRAM
IBM0364164PT3C-260	ETC	获取价格	x16 SDRAM
IBM0364164PT3C-360	ETC	获取价格	x16 SDRAM
IBM0364404CT3-12	IBM	获取价格	Synchronous DRAM, 16MX4, 8ns, CMOS, PDSO54

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