Datasheet > IBM0364404CT3C-10

IBM0364404CT3C-10

更新时间： 2024-01-22 19:34:45

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
73页	857K
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x4 SDRAM

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IBM0364804 IBM0364164

IBM0364404 IBM03644B4

64Mb Synchronous DRAM - Die Revision C

Features

• Programmable Wrap: Sequential or Interleave

• High Performance:

-68 -75A, -260, -360, -10,

CL=3 CL=3 CL=2 CL=3 CL=3

• Multiple Burst Read with Single Write Option

Units

• Automatic and Controlled Precharge Command

Clock Frequency

Clock Cycle

150 133 100 100 100 MHz

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard or Low Power operation

• 4096 refresh cycles/64ms

6.67 7.5

—

AC Clock Access Time

5.4

—

1. Terminated load. See AC Characteristics on page 41.

2. Unterminated load. See AC Characteristics on page 41.

• Single Pulsed RAS Interface

• Random Column Address every CLK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by A12/A13 (Bank Select)

• Programmable CAS Latency: 2, 3

• Package: 54-pin 400 mil TSOP-Type II

2 High Stack TSOJ

• Programmable Burst Length: 1, 2, 4, 8, full-page

Description

The IBM0364404, IBM0364804, and IBM0364164

are four-bank Synchronous DRAMs organized as

4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and

1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,

a stacked version of the x4 component, is also

offered. These synchronous devices achieve high-

speed data transfer rates of up to 150MHz by

employing a pipeline chip architecture that synchro-

nizes the output data to a system clock. The chip is

fabricated with IBM’s advanced 64Mbit single tran-

sistor CMOS DRAM process technology.

and two bank select addresses (A12, A13) are

strobed with RAS. Ten column addresses (A0-A9)

plus bank select addresses and A10 are strobed

with CAS. Column address A9 is dropped on the x8

device and column addresses A8 and A9 are

dropped on the x16 device. Access to the lower or

upper DRAM in a stacked device is controlled by

CS0 and CS1, respectively.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A9

during a mode register set cycle. In addition, it is

possible to program a multiple burst sequence with

single write cycle for write through cache operation.

The device is designed to comply with all JEDEC

standards set for synchronous DRAM products,

both electrically and mechanically. All of the control,

address, and data input/output (I/O or DQ) circuits

are synchronized with the positive edge of an exter-

nally supplied clock.

Operating the four memory banks in an interleave

fashion allows random access operation to occur at

a higher rate than is possible with standard DRAMs.

A sequential and gapless data rate of up to 150MHz

is possible depending on burst length, CAS latency,

and speed grade of the device. Simultaneous opera-

tion of both decks of a stacked device is allowed,

depending on the operation being done. Auto

Refresh (CBR), Self Refresh, and Low Power opera-

tion are supported.

RAS, CAS, WE, and CS are pulsed signals which

are examined at the positive edge of each externally

applied clock (CLK). Internal chip operating modes

are defined by combinations of these signals and a

command decoder initiates the necessary timings

for each operation. A fourteen bit address bus

accepts address data in the conventional RAS/CAS

multiplexing style. Twelve row addresses (A0-A11)

Use is further subject to the provisions at the end of this document.

19L3265.E35856B

01/00

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与IBM0364404CT3C-10相关器件

型号	品牌	获取价格	描述	数据表
IBM0364404CT3C-260	ETC	获取价格	x4 SDRAM
IBM0364404CT3C-360	ETC	获取价格	x4 SDRAM
IBM0364404CT3C-75A	ETC	获取价格	x4 SDRAM
IBM0364444CT3-80	ETC	获取价格	x4 SDRAM
IBM03644B4CT3A-10	ETC	获取价格	x4 SDRAM Module
IBM03644B4CT3A-360	IBM	获取价格	Synchronous DRAM Module, 16MX4, 6ns, CMOS, PDSO54, 0.400 INCH, 2 HIGH STACK, TSOJ2-54
IBM03644B4CT3A-365	IBM	获取价格	Synchronous DRAM Module, 16MX4, 6.5ns, CMOS, PDSO54, 0.400 INCH, 2 HIGH STACK, TSOJ2-54
IBM03644B4CT3A-370	ETC	获取价格	x4 SDRAM Module
IBM03644B4CT3B-10	IBM	获取价格	Synchronous DRAM Module, 16MX4, 9ns, CMOS, PDSO54, 0.400 INCH, 2 HIGH STACK, PLASTIC, TSOJ
IBM03644B4CT3B-360	IBM	获取价格	Synchronous DRAM Module, 16MX4, 6ns, CMOS, PDSO54, 0.400 INCH, 2 HIGH STACK, PLASTIC, TSOJ

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