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HYMD216726C6-H PDF预览

HYMD216726C6-H

更新时间: 2024-11-11 05:37:15
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
16页 264K
描述
Unbuffered DDR SO-DIMM

HYMD216726C6-H 技术参数

生命周期:Obsolete零件包装代码:DMA
包装说明:DIMM, DIMM184针数:184
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
Is Samacsys:N访问模式:SINGLE BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N184内存密度:1207959552 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:184字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM184封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:2.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.1 A
子类别:DRAMs最大压摆率:1.625 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

HYMD216726C6-H 数据手册

 浏览型号HYMD216726C6-H的Datasheet PDF文件第2页浏览型号HYMD216726C6-H的Datasheet PDF文件第3页浏览型号HYMD216726C6-H的Datasheet PDF文件第4页浏览型号HYMD216726C6-H的Datasheet PDF文件第5页浏览型号HYMD216726C6-H的Datasheet PDF文件第6页浏览型号HYMD216726C6-H的Datasheet PDF文件第7页 
16Mx72 bits  
Unbuffered DDR SO-DIMM  
HYMD216726C(L)6-M/K/H/L  
DESCRIPTION  
Hynix HYMD216726C(L)6-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line  
Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216726C(L)6-M/K/  
H/L series consists of eighteen 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.  
Hynix HYMD216726C(L)6-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of  
industry standard. It is suitable for easy interchange and addition.  
Hynix HYMD216726C(L)6-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous  
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control  
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on  
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high  
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable  
latencies and burst lengths allow variety of device operation in high performance memory system.  
Hynix HYMD216726C(L)6-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is  
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify  
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.  
FEATURES  
128MB (16M x72) Unbuffered DDR DIMM based on  
16Mx16 DDR SDRAM  
Data(DQ), Data strobes and Write masks latched on  
both rising and falling edges of the clock  
JEDEC Standard 184-pin dual in-line memory module  
(DIMM)  
Data inputs on DQS centers when write (centered  
DQ)  
Error Check Correction (ECC) Capability  
Data strobes synchronized with output data for read  
and input data for write  
2.5V +/- 0.2V VDD and VDDQ Power supply  
Programmable CAS Latency 2 / 2.5 supported  
All inputs and outputs are compatible with SSTL_2  
interface  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
Fully differential clock operations (CK & /CK) with  
100MHz/125MHz/133MHz  
tRAS Lock-out function supported  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
Internal four bank operations with single pulsed RAS  
Auto refresh and self refresh supported  
8192refresh cycles / 64ms  
ORDERING INFORMATION  
Part No.  
Power Supply  
Clock Frequency  
Interface  
Form Pactor  
HYMD216726C(L)6-M  
HYMD216726C(L)6-K  
HYMD216726C(L)6-H  
HYMD216726C(L)6-L  
133MHz (*DDR266:2-2-2)  
133MHz(*DDR266A)  
133MHz(*DDR266B)  
100MHz(*DDR200)  
VDD=2.5V  
VDDQ=2.5V  
184pin Unbuffered DIMM  
5.25 x 1.25 x 0.15 inch  
SSTL_2  
* JEDEC Defined Specifications compliant  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.1 / Mar. 2003  
1

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