Datasheet > HY57V56820T-HP

HY57V56820T-HP

更新时间： 2024-11-30 23:57:11

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
13页	153K
描述
x8 SDRAM

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HY57V56820T-HP 数据手册

HY57V56820(L)T

4Banks x 8M x 8Bit Synchronous DRAM

DESCRIPTION

The HY57V56820T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications

which require large memory density and high bandwidth. HY57V56820 is organized as 4 banks of 8,388,608x8.

HY57V56820T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3V ± 0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequential Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM.

Internal four banks operation

•

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V56820T-HP

HY57V56820T-H

HY57V56820T-8

HY57V56820T-P

HY57V56820T-S

HY57V56820LT-HP

HY57V56820LT-H

HY57V56820LT-8

HY57V56820LT-P

HY57V56820LT-S

133MHz

125MHz

100MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits

x16

LVTTL

400mil 54pin TSOP II

Lower

Power

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.8/Nov. 01

12 3 4 5 6 7...13

中文翻译

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与HY57V56820T-HP相关器件

型号	品牌	获取价格	描述	数据表
HY57V56820T-P	HYNIX	获取价格	Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V56820T-S	ETC	获取价格	x8 SDRAM
HY57V641610TC-10	ETC	获取价格	x16 SDRAM
HY57V641610TC-12	ETC	获取价格	x16 SDRAM
HY57V641610TC-15	ETC	获取价格	x16 SDRAM
HY57V641611LTC-8	HYNIX	获取价格	Synchronous DRAM, 4MX16, CMOS, TSOP2
HY57V641611TC-10	ETC	获取价格	x16 SDRAM
HY57V641611TC-7	ETC	获取价格	x16 SDRAM
HY57V641611TC-8	ETC	获取价格	x16 SDRAM
HY57V641620ELT-5	HYNIX	获取价格	Synchronous DRAM, 4MX16, 4.5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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