HY57V641620ESTP-HI

更新时间： 2024-02-04 18:55:03

品牌	Logo	应用领域
海力士 - HYNIX		存储内存集成电路光电二极管动态存储器时钟
页数	文件大小	规格书
13页	116K
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HY57V641620ESTP-HI 数据手册

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64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O

Document Title

4Bank x 1M x 16bits Synchronous DRAM

Revision History

Revision No.

History

Draft Date

Remark

First Version Release

1.0

Nov. 2004

1. Changed tOH: 2.0 --> 2.5

[tCK = 7 & 7.5 (CL3) Product]

1. Changed Input High/Low Voltage (Page 08)

2. Changed DC characteristics (Page 09)

- IDD2NS: 18mA -> 15mA

- IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA

[Speed 200 / 166 / 143 / 133MHz]

3. Changed Clock High / Low pulse width Time (Page 11)

4. Changed tAC Time (Page11)

1.1

1.2

Dec. 2004

5. Changed tRRD Time (Page12)

1. Corrected Revision No.: 2.0 -> 1.1

2. Deleted Remark at Revision History

3. Corrected AC OPERATING CONDITION

- CL 50pF -> 30pF

4. Changed DC OPERATING CONDITION

- VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0

- VIL MIN VSSQ-2.0 -> -0.3

1.3

1.4

1.5

1. Modified note for Super Low Power in ORDERING INFORMATION

1. Corrected PIN ASSIGNMENT A12 to NC

Jan. 2005

Feb. 2005

1. Corrected comments for overshoot and undershoot

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 1.5 / Feb. 2005

12 3 4 5 6 7...13

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