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HY57V561620CLTP-7 PDF预览

HY57V561620CLTP-7

更新时间: 2024-11-01 04:12:15
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
12页 214K
描述
4 Banks x 4M x 16Bit Synchronous DRAM

HY57V561620CLTP-7 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.73
Is Samacsys:N访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):143 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e6长度:22.238 mm
内存密度:268435456 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.194 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.22 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Bismuth (Sn/Bi)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:10.16 mm
Base Number Matches:1

HY57V561620CLTP-7 数据手册

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HY57V561620C(L)T(P)  
4 Banks x 4M x 16Bit Synchronous DRAM  
DESCRIPTION  
The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications  
which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.  
HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs  
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input  
and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by  
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or  
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or  
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3±0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
8192 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin  
pitch (Leaded Package or Lead Free Package)  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of system  
clock  
Data mask function by UDQM, LDQM  
Internal four banks operation  
Programmable CAS Latency ; 2, 3 Clocks  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
400mil 54pin TSOP II  
HY57V561620C(L)T(P)-6  
HY57V561620C(L)T(P)-7  
HY57V561620C(L)T(P)-K  
HY57V561620C(L)T(P)-H  
HY57V561620C(L)T(P)-8  
HY57V561620C(L)T(P)-P  
HY57V561620C(L)T(P)-S  
166MHz  
143MHz  
133MHz  
133MHz  
125MHz  
100MHz  
100MHz  
(Normal)  
/
Low Power  
(Leaded)  
/
Lead Free  
4Banks x 4Mbits x16  
LVTTL  
Note :  
1. HY57V561620CT Series  
: Nomal power & Leaded 54Pin TSOP II  
2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II  
3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II  
4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev. 0.5 / June 2004  
1

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