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HY57V561620CT-PI PDF预览

HY57V561620CT-PI

更新时间: 2024-11-24 13:00:27
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
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HY57V561620CT-PI 数据手册

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HY57V561620(L)T  
4Banks x 4M x 16Bit Synchronous DRAM  
DESCRIPTION  
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications  
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.  
The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and  
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3V ± 0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
8192 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm  
of pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 and Full Page for Sequential Burst  
- 1, 2, 4 and 8 for Interleave Burst  
Programmable CAS Latency ; 2, 3 Clocks  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by UDQM and LDQM  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V561620T-HP  
HY57V561620T-H  
HY57V561620T-8  
HY57V561620T-P  
HY57V561620T-S  
HY57V561620LT-HP  
HY57V561620LT-H  
HY57V561620LT-8  
HY57V561620LT-P  
HY57V561620LT-S  
133MHz  
133MHz  
125MHz  
100MHz  
100MHz  
133MHz  
133MHz  
125MHz  
100MHz  
100MHz  
Normal  
4Banks x 4Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
Lower  
Power  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Revision 1.8 / Apr.01  

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