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HX6218DBHC PDF预览

HX6218DBHC

更新时间: 2024-01-16 06:39:34
品牌 Logo 应用领域
其他 - ETC 先进先出芯片
页数 文件大小 规格书
16页 159K
描述
x18 Synchronous FIFO

HX6218DBHC 技术参数

生命周期:Obsolete包装说明:GQFF,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.68
最长访问时间:30 ns周期时间:34 ns
JESD-30 代码:S-CQFP-F132长度:24.13 mm
内存密度:36864 bit内存宽度:18
功能数量:1端子数量:132
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX18
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:GQFF封装形状:SQUARE
封装形式:FLATPACK, GUARD RING并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:2.7686 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.635 mm
端子位置:QUAD宽度:24.13 mm
Base Number Matches:1

HX6218DBHC 数据手册

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Aerospace Electronics  
FIFO—SOI  
HX6409  
HX6218  
HX6136  
FEATURES  
• 1K x 36, 2K x 18, 4K x 9 Organizations  
OTHER  
• Fabricated with RICMOSIV Silicon on Insulator  
• Read/Write Cycle Times  
(SOI) 0.8 µm Process (Leff = 0.65µm)  
<35 ns (-55° to 125°C)  
• Expandable in Width  
RADIATION  
• Supports Free-Running 50% Duty Cycle Clock  
• Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags  
• Parity Generation/Checking  
• Total Dose Hardness through 1x106 rad(SiO2)  
• Neutron Hardness through 1x1014 cm-2  
• Dynamic and Static Transient Upset Hardness  
through 1x109 rad(Si)/s  
• Fully Asynchronous with Simultaneous  
Read and Write Operation  
• Dose Rate Survivability through 1x1011 rad(Si)/s  
• Soft Error Rate of <1x10-10 upsets/bit-day  
• No Latchup  
• Output Enable (OE)  
• CMOS or TTL Compatible I/O  
• Single 5 V ± 10% Power Supply  
• Various Flat Pack Options  
GENERAL DESCRIPTION  
The HX6409, HX6218, and HX6136 are high speed, low-  
power, first-in first-out memories with clocked read and  
write interfaces. The HX6409 is a 4096 word by 9 bit  
memory array, the HX6218 is a 2048 word by 18 bit  
memory array, and the HX6136 is a 1024 word by 36 bit  
memory array. The FIFOs support width expansion while  
depthexpansionrequiresexternallogiccontrolusingstate  
machinetechniques.Featuresincludeprogrammablepar-  
ity control, an empty/full flag, a quarter/three quarter full  
flag, a half full flag and an error flag.  
The output port is controlled in a similar manner by a free-  
running read clock (CKR) and a read enable pin (  
). In  
ENR  
addition, the three FIFOs have an output enable pin (  
and a master reset pin (  
MR  
)
OE  
). The read (CKR) and write  
(CKW) clocks may be tied together for single-clock  
operation or the two clocks may be run independently for  
asynchronous read/write applications. Clock frequencies  
up to 30 MHz are achievable in the three configurations.  
Honeywell’s enhanced SOI RICMOS™ IV (Radiation In-  
sensitive CMOS) technology is radiation hardened through  
the use of advanced and proprietary design, layout and  
process hardening techniques. The FIFO is fabricated with  
Honeywell’s radiation hardened technology, and is de-  
signed for use in systems operating in radiation environ-  
ments. The SOI RICMOS™ IV process is a 5-volt, SIMOX  
CMOS technology with a 150 Å gate oxide and a minimum  
drawn feature size of 0.8 µm, (0.65 µm effective gate  
array—Leff). Additional features include tungsten via plugs,  
Honeywell’s proprietary SHARP planarization process,  
andalightlydopeddrain(LDD)structureforimprovedshort  
channel reliability.  
These FIFOs provide solutions for a wide variety of data  
buffering needs, including high-speed data acquisition,  
multiprocessor interfaces, and communications buffer-  
ing. These FIFOs have separate input and output ports  
that are controlled by separate clock and enable sig-  
nals. The input port is controlled by a free running clock  
(CKW) and a write enable pin  
. When  
is  
ENW  
ENW  
asserted, data is written into the FIFO on the rising edge  
of the CKW signal. While is held active, data is  
ENW  
continually written into the FIFO on each CKW cycle.  
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com  

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