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HV57708T PDF预览

HV57708T

更新时间: 2024-09-16 21:18:59
品牌 Logo 应用领域
超科 - SUPERTEX 驱动接口集成电路
页数 文件大小 规格书
5页 38K
描述
EL Driver, 64-Segment, CMOS

HV57708T 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.69
数据输入模式:PARALLEL显示模式:DOT MATRIX
接口集成电路类型:EL DISPLAY DRIVERJESD-30 代码:X-XUUC-N80
复用显示功能:NO功能数量:1
区段数:64端子数量:80
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
认证状态:Not Qualified表面贴装:YES
技术:CMOS端子形式:NO LEAD
端子位置:UPPER最小 fmax:8 MHz
Base Number Matches:1

HV57708T 数据手册

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HV57708  
32 MHz, 64-Channel Serial To Parallel Converter  
With Push-Pull Outputs  
Ordering Information  
Package Options  
80 Lead Quad  
Device  
80 Lead Quad  
80 Lead Quad  
Ceramic Gullwing  
Ceramic Gullwing  
Plastic Gullwing  
Die  
TAB**  
(MIL-STD-883 Processed*)  
(MIL-STD-883 Processed*)  
HV57708  
HV57708DG  
HV57708PG  
HV57708X  
RBHV57708DG  
HV57708T  
* For Hi-Rel process flows, refer to page 5-3 of the Databook.  
** Dual die on tape for 128 output.  
Features  
General Description  
The HV577 is a low-voltage serial to high-voltage parallel con-  
verter with push-pull outputs. This device has been designed for  
useasadriverforelectroluminescentdisplays.Itcanalsobeused  
in any application requiring multiple output high-voltage current  
sourcing and sinking capability such as driving plasma panels,  
vacuum fluorescent displays, or large matrix LCD displays.  
Processed with HVCMOS® technology  
5V CMOS logic  
Output voltages up to 80V  
Low power level shifting  
24MHz equivalent data rate  
Latched data outputs  
The device has 4 parallel 16-bit shift registers, permitting data  
rates 4X the speed of one ( they are clocked together). There are  
also 64 latches and control logic to perform the polarity select and  
blanking of the outputs. HVout1 is connected to the first stage of  
the first shift register through the polarity and blanking logic. Data  
is shifted through the shift registers on the logic low to high  
transition of the clock. The DIR pin causes CCW shifting when  
connected to GND, and CW shifting when connected to VDD. A  
data output buffer is provided for cascading devices. This output  
reflects the current status of the last bit of the shift register  
(HVOUT64). Operation of the shift register is not affected by the LE  
(latch enable), BL (blanking), or the POL (polarity) inputs. Trans-  
fer of data from the shift registers to the latches occurs when the  
LE (latch enable) input is high. The data in the latches is stored  
when LE is low.  
Forward and reverse shifting options (DIR pin)  
Diode to VPP allows efficient power recovery  
Outputs may be hot switched  
Hi-Rel processing available  
Absolute Maximum Ratings  
1
Supply voltage, VDD  
-0.5V to +7.5V  
1
Output voltage, VPP  
-0.5V to +90V  
-0.3V to VDD +0.3V  
1.5A  
Logic input levels1  
Ground current2  
Continuous total power dissipation3  
Plastic  
Ceramic  
1200mW  
1900mW  
Operating temperature range  
Plastic  
Ceramic  
-40 to 85°C  
-55°C to 125°C  
Storage temperature range  
-65°C to +150°C  
260°C  
Lead temperature 1.6mm (1/16 inch)  
from case for 10 seconds  
Notes:  
1. All voltages are referenced to GND.  
2. Limited by the total power dissipated in the package.  
3. For operation above 25°C ambient derate linearly to maximum operating  
temperature at 20mW/°C for plastic and at 19mW/°C for ceramic.  
For detailed circuit and application information, please refer  
to application note AN-H3.  
12-91  

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