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HSP45116AVC-52 PDF预览

HSP45116AVC-52

更新时间： 2024-02-11 05:01:57
品牌 Logo 应用领域
英特矽尔 - INTERSIL 振荡器外围集成电路时钟
页数 文件大小 规格书
18页 132K
描述
Numerically Controlled Oscillator/Modulator

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中文翻译

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HSP45116AVC-52 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：MQFP包装说明：QFP, QFP160,1.2SQ
针数：160Reach Compliance Code：compliant
ECCN代码：3A001.A.3HTS代码：8542.39.00.01
风险等级：5.79边界扫描：NO
最大时钟频率：52 MHz外部数据总线宽度：19
JESD-30 代码：S-PQFP-G160JESD-609代码：e3
长度：28 mm低功率模式：YES
湿度敏感等级：3端子数量：160
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：20封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP160,1.2SQ
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：245电源：5 V
认证状态：Not Qualified座面最大高度：4.1 mm
子类别：DSP Peripherals最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：28 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：1

HSP45116AVC-52 数据手册

 浏览型号HSP45116AVC-52的Datasheet PDF文件第2页浏览型号HSP45116AVC-52的Datasheet PDF文件第3页浏览型号HSP45116AVC-52的Datasheet PDF文件第4页浏览型号HSP45116AVC-52的Datasheet PDF文件第5页浏览型号HSP45116AVC-52的Datasheet PDF文件第6页浏览型号HSP45116AVC-52的Datasheet PDF文件第7页 
HSP45116  
Data Sheet  
May 1999  
File Number 2485.7  
Numerically Controlled  
Oscillator/Modulator  
Features  
• NCO and CMAC on One Chip  
The Intersil HSP45116 combines a high performance  
quadrature Numerically Controlled Oscillator (NCO) and a  
high speed 16-bit Complex Multiplier/Accumulator (CMAC)  
on a single IC. This combination of functions allows a  
complex vector to be multiplied by the internally generated  
(cos, sin) vector for quadrature modulation and  
• 15MHz, 25.6MHz, 33MHz Versions  
• 32-Bit Frequency Control  
• 16-Bit Phase Modulation  
• 16-Bit CMAC  
• 0.008Hz Tuning Resolution at 33MHz  
• Spurious Frequency Components < -90dBc  
• Fully Static CMOS  
demodulation. As shown in the Block Diagram, the  
HSP45116 is divided into three main sections. The  
Phase/Frequency Control Section (PFCS) and the  
Sine/Cosine Section together form a complex NCO. The  
CMAC multiplies the output of the Sine/ Cosine Section with  
an external complex vector.  
Applications  
• Frequency Synthesis  
• Modulation - AM, FM, PSK, FSK, QAM  
• Demodulation, PLL  
The inputs to the Phase/Frequency Control Section consist  
of a microprocessor interface and individual control lines.  
The phase resolution of the PFCS is 32 bits, which results in  
frequency resolution better than 0.008Hz at 33MHz. The  
output of the PFCS is the argument of the sine and cosine.  
The spurious free dynamic range of the complex sinusoid is  
greater than 90dBc.  
• Phase Shifter  
• Polar to Cartesian Conversions  
Ordering Information  
The output vector from the Sine/Cosine Section is one of the  
inputs to the Complex Multiplier/Accumulator. The CMAC  
multiplies this (cos, sin) vector by an external complex vector  
and can accumulate the result. The resulting complex vectors  
are available through two 20-bit output ports which maintain  
the 90dB spectral purity. This result can be accumulated  
internally to implement an accumulate and dump filter.  
TEMP.  
o
PART NUMBER  
HSP45116VC-15  
HSP45116VC-25  
HSP45116GC-15  
HSP45116GC-25  
HSP45116GC-33  
HSP45116GI-15  
HSP45116GI-25  
HSP45116GI-33  
RANGE ( C) PACKAGE  
PKG. NO.  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
160 Ld MQFP Q160.28x28  
160 Ld MQFP Q160.28x28  
145 Ld CPGA G145.A  
145 Ld CPGA G145.A  
145 Ld CPGA G145.A  
A quadrature down converter can be implemented by  
loading a center frequency into the Phase/Frequency  
Control Section. The signal to be down converted is the  
Vector Input of the CMAC, which multiplies the data by the  
rotating vector from the Sine/Cosine Section. The resulting  
complex output is the down converted signal.  
-40 to 85 145 Ld CPGA G145.A  
-40 to 85 145 Ld CPGA G145.A  
-40 to 85 145 Ld CPGA G145.A  
HSP45116GM-15/883 -55 to 125 145 Ld CPGA G145.A  
HSP45116GM-25/883 -55 to 125 145 Ld CPGA G145.A  
HSP45116AVC-52  
0 to 70  
160 Ld MQFP Q160.28x28  
† This part has its own data sheet under HSP45116A, AnswerFAX  
document no. 4156.  
Block Diagram  
VECTOR INPUT  
R
I
SINE/  
COSINE  
ARGUMENT  
MICROPROCESSOR  
PHASE/  
SIN  
INTERFACE  
SINE/  
COSINE  
SECTION  
FREQUENCY  
CMAC  
CONTROL  
COS  
INDIVIDUAL  
SECTION  
CONTROL SIGNALS  
R
I
VECTOR OUTPUT  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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