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HSP43124SI-40 PDF预览

HSP43124SI-40

更新时间: 2024-11-13 22:16:43
品牌 Logo 应用领域
英特矽尔 - INTERSIL 过滤器外围集成电路光电二极管LTE时钟
页数 文件大小 规格书
17页 147K
描述
Serial I/O Filter

HSP43124SI-40 数据手册

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HSP43124  
Data Sheet  
May 1999  
File Number 3555.6  
Serial I/O Filter  
Features  
The Serial I/O Filter is a high performance filter engine that is  
ideal for off loading the burden of filter processing from a  
DSP microprocessor. It supports a variety of multistage filter  
configurations based on a user programmable filter and fixed  
coefficient halfband filters. These configurations include a  
programmable FIR filter of up to 256 taps, a cascade of from  
one to five halfband filters, or a cascade of halfband filters  
followed by a programmable FIR. The half band filters each  
decimate by a factor of two, and the FIR filter decimates from  
one to eight. When all six filters are selected, a maximum  
decimation of 256 is provided.  
• 45MHz Clock Rate  
• 256 Tap Programmable FIR Filter  
• 24-Bit Data, 32-Bit Coefficients  
• Cascade of up to 5 Half Band Filters  
• Decimation from 1 to 256  
Two Pin Interface for Down Conversion by F /4  
S
• Multiplier for Mixing or Scaling Input with an External  
Source  
• Serial I/O Compatible with Most DSP Microprocessors  
For digital tuning applications, a separate multiplier is  
provided which allows the incoming data stream to be  
multiplied, or mixed, by a user supplied mix factor. A two pin  
interface is provided for serially loading the mix factor from  
an external source or selecting the mix factor from an on-  
board ROM. The on-board ROM contains samples of a  
sinusoid capable of spectrally shifting the input data by one  
Applications  
• Low Cost FIR Filter  
• Filter Co-Processor  
• Digital Tuner  
quarter of the sample rate, F /4. This allows the chip to  
function as a digital down converter when the filter stages  
are configured as a low-pass filter.  
S
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER  
HSP43124PC-45  
HSP43124PC-33  
HSP43124SC-45  
HSP43124SC-33  
HSP43124SI-40  
RANGE ( C)  
PACKAGE  
28 Ld PDIP  
The serial interface for3- input and output data is compatible  
with the serial ports of common DSP microprocessors.  
Coefficients and configuration data are loaded over a  
bidirectional eight bit interface.  
0 to 70  
E28.6  
0 to 70  
28 Ld PDIP  
28 Ld SOIC  
28 Ld SOIC  
28 Ld SOIC  
E28.6  
M28.3  
M28.3  
M28.3  
0 to 70  
0 to 70  
-40 to 85  
Block Diagram  
DIN  
DOUT  
SCLK  
HALF  
BAND  
FILTER  
#1  
HALF  
BAND  
FILTER  
#2  
HALF  
BAND  
FILTER  
#5  
SYNCOUT  
CLKOUT  
SYNCIN  
MXIN  
SYNCMX  
CONTROL  
INTERFACE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1

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