Datasheet > HSP43168JC-40

HSP43168JC-40

更新时间： 2024-09-25 22:19:59

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路 LTE 时钟
页数	文件大小	规格书
26页	327K
描述
Dual FIR Filter

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HSP43168JC-40 数据手册

HSP43168

Data Sheet

November 1999

File Number 2808.8

Dual FIR Filter

Features

The HSP43168 Dual FIR Filter consists of two independent

8-tap FIR ﬁlters. Each ﬁlter supports decimation from 1 to 16

and provides on-board storage for 32 sets of coefﬁcients.

The Block Diagram shows two FIR cells each fed by a

separate coefﬁcient bank and one of two separate inputs.

The outputs of the FIR cells are either summed or

multiplexed by the MUX/Adder. The compute power in the

FIR Cells can be conﬁgured to provide quadrature ﬁltering,

complex ﬁltering, 2-D convolution, 1-D/2-D correlations, and

interpolating/decimating ﬁlters.

• Two Independent 8-Tap FIR Filters Conﬁgurable as a

Single 16-Tap FIR

• 10-Bit Data and Coefﬁcients

• On-Board Storage for 32 Programmable Coefficient Sets

• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit

Data and Coefﬁcients

• Programmable Decimation to 16

• Programmable Rounding on Output

• Standard Microprocessor Interface

The FIR cells take advantage of symmetry in FIR

coefﬁcients by pre-adding data samples prior to

multiplication. This allows an 8-tap FIR to be implemented

using only 4 multipliers per ﬁlter cell. These cells can be

conﬁgured as either a single 16-tap FIR ﬁlter or dual 8-tap

FIR ﬁlters. Asymmetric ﬁltering is also supported.

Applications

• Quadrature, Complex Filtering

• Image Processing

• Polyphase Filtering

• Adaptive Filtering

Decimation of up to 16 is provided to boost the effective number

of filter taps from 2 to 16 times. Further, the Decimation

Registers provide the delay necessary for fractional data

conversion and 2-D filtering with kernels to 16 x16.

Ordering Information

TEMP.

The ﬂexibility of the Dual is further enhanced by 32 sets of

user programmable coefﬁcients. Coefﬁcient selection may

be changed asynchronously from clock to clock. The ability

to toggle between coefﬁcient sets further simpliﬁes

applications such as polyphase or adaptive ﬁltering.

PART NUMBER RANGE ( C)

PACKAGE

PKG. NO.

HSP43168VC-33

HSP43168VC-40

HSP43168VC-45

HSP43168JC-33

HSP43168JC-40

HSP43168JC-45

HSP43168JI-40

HSP43168GC-45

0 to 70

-40 to 85

0 to 70

100 Ld MQFP Q100.14x20

84 Ld PLCC

84 Ld CPGA

N84.1.15

G84.A

The HSP43168 is a low power fully static design

implemented in an advanced CMOS process. The

conﬁguration of the device is controlled through a standard

microprocessor interface.

Block Diagram

CIN0 - 9

CONTROL/

CONFIGURATION

A0 - 8

CSEL0 - 4

COEFFICIENT

BANK A

COEFFICIENT

BANK B

INA0 - 9

FIR CELL A

FIR CELL B

MUX

INB0 - 9/

OUT0 - 8

MUX/

ADDER

OUT9 - 27

OEL

OEH

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4 5 6 7...26

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与HSP43168JC-40相关器件

型号	品牌	获取价格	描述	数据表
HSP43168JC-45	RENESAS	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84, PLASTIC, LCC-84
HSP43168JC-45	INTERSIL	获取价格	Dual FIR Filter
HSP43168JC-45	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84
HSP43168JI-40	INTERSIL	获取价格	Dual FIR Filter
HSP43168VC-33	INTERSIL	获取价格	Dual FIR Filter
HSP43168VC-33	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQFP100
HSP43168VC-40	INTERSIL	获取价格	Dual FIR Filter
HSP43168VC-40	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQFP100
HSP43168VC-45	INTERSIL	获取价格	Dual FIR Filter
HSP43168VC-45	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQFP100

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