Datasheet > HSP43168GM-33/883

HSP43168GM-33/883

更新时间： 2024-11-13 22:13:11

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路输出元件输入元件 LTE 时钟
页数	文件大小	规格书
10页	172K
描述
Dual FIR Filter

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HSP43168GM-33/883 数据手册

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HSP43168/883

Data Sheet

May 1999

FN3177.3

Dual FIR Filter

Features

The HSP43168/883 Dual FIR Filter consists of two

independent 8-tap FIR filters. Each filter supports

• This Circuit is Processed in Accordance to MIL-STD-883

and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

decimation from 1 to 16 and provides on-board storage for

32 sets of coefficients. The Block Diagram shows two FIR

cells each fed by a separate coefficient bank and one of two

separate inputs. The outputs of the FIR cells are either

summed or multiplexed by the MUX/Adder. The compute

power in the FIR Cells can be configured to provide

quadrature filtering, complex filtering, 2-D convolution, 1-

D/2-D correlations, and interpolating/decimating filters.

• Two Independent 8-Tap FIR Filters Configurable as a

Single 16-Tap FIR

• 10-Bit Data and Coefficients

• On-Board Storage for 32 Programmable

Coefficient Sets

• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or

10 x 20-Bit Data and Coefficients

The FIR cells take advantage of symmetry in FIR

coefficients by pre-adding data samples prior to

multiplication. This allows an 8-tap FIR to be implemented

using only 4 multipliers per filter cell. These cells can be

configured as either a single 16-tap FIR filter or dual 8-tap

FIR filters. Asymmetric filtering is also supported.

• Programmable Decimation to 16

• Programmable Rounding on Output

• Standard Microprocessor Interface

• 33MHz, 25.6MHz Versions

Decimation of up to 16 is provided to boost the effective number

of filter taps from 2 to 16 times. Further, the Decimation

Registers provide the delay necessary for fractional data

conversion and 2-D filtering with kernels to 16 x 16.

Applications

• Quadrature, Complex Filtering

• Correlation

The flexibility of the dual is further enhanced by 32 sets of

user programmable coefficients. Coefficient selection may

be changed asynchronously from clock to clock. The ability

to toggle between coefficient sets further simplifies

applications such as polyphase or adaptive filtering.

• Image Processing

• PolyPhase Filtering

• Adaptive Filtering

Ordering Information

The HSP43168 is a low power fully static design

implemented in an advanced CMOS process. The

configuration of the device is controlled through a standard

microprocessor interface.

TEMP.

PKG.

NO.

PART NUMBER

HSP43168GM-25/883

HSP43168GM-33/883

RANGE ( C) PACKAGE

-55 to 125 84 Ld PGA

G84.A

Block Diagram

CIN0 - 9

CONTROL/

CONFIGURATION

A0 - 8

CSEL0 - 4

COEFFICIENT

BANK A

COEFFICIENT

BANK B

INA0 - 9

FIR CELL A

FIR CELL B

MUX

INB0 - 9/

OUT0 - 8

MUX/

ADDER

OUT9 - 27

OEL

OEH

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

12 3 4 5 6 7...10

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与HSP43168GM-33/883相关器件

型号	品牌	获取价格	描述	数据表
HSP43168JC-33	INTERSIL	获取价格	Dual FIR Filter
HSP43168JC-33	RENESAS	获取价格	Dual FIR Filter; PLCC84; Temp Range: See Datasheet
HSP43168JC-33Z	INTERSIL	获取价格	Dual FIR Filter
HSP43168JC-40	INTERSIL	获取价格	Dual FIR Filter
HSP43168JC-40	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84
HSP43168JC-40	RENESAS	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84
HSP43168JC-45	RENESAS	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84, PLASTIC, LCC-84
HSP43168JC-45	INTERSIL	获取价格	Dual FIR Filter
HSP43168JC-45	ROCHESTER	获取价格	10-BIT, DSP-DIGITAL FILTER, PQCC84
HSP43168JI-40	INTERSIL	获取价格	Dual FIR Filter

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