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HMP125S6EFR8C-C4 PDF预览

HMP125S6EFR8C-C4

更新时间: 2024-11-06 10:54:11
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
23页 516K
描述
200pin Unbuffered DDR2 SDRAM SO-DIMMs

HMP125S6EFR8C-C4 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:SODIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.6Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.45 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):266 MHz
I/O 类型:COMMONJESD-30 代码:R-XZMA-N200
长度:67.6 mm内存密度:17179869184 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:268435456 words
字数代码:256000000工作模式:SYNCHRONOUS
最高工作温度:65 °C最低工作温度:
组织:256MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM200,24封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:3.8 mm
自我刷新:YES最大待机电流:0.16 A
子类别:DRAMs最大压摆率:1.68 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.6 mm
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:20
宽度:30 mmBase Number Matches:1

HMP125S6EFR8C-C4 数据手册

 浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第2页浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第3页浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第4页浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第5页浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第6页浏览型号HMP125S6EFR8C-C4的Datasheet PDF文件第7页 
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version E  
This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2  
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version E based  
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-  
try standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate 2 Synchronous  
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power  
Supply  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
All inputs and outputs are compatible with SSTL_1.8  
interface  
Serial presence detect with EEPROM  
Posted CAS  
DDR2 SDRAM Package: 60 ball(x8), 84 ball(x16)  
FBGA  
Programmable CAS Latency 3,4,5, and 6  
OCD (Off-Chip Driver Impedance Adjustment) and  
ODT (On-Die Termination)  
67.60 x 30.00 mm form factor  
RoHS compliant & Halogen-free  
Fully differential clock operations (CK & CK)  
* This product is in compliance with the directive pertaining of RoHS  
ORDERING INFORMATION  
# of  
DRAMs  
# of  
ranks  
Part Name  
Density  
Organization  
Materials  
HMP164S6EFR6C-C4/Y5/S5/S6  
HMP112S6EFR6C-C4/Y5/S5/S6  
HMP125S6EFR8C-C4/Y5/S5/S6  
512MB  
1GB  
64Mx64  
128Mx64  
256Mx64  
4
8
1
2
2
Halogen free  
Halogen free  
Halogen free  
2GB  
16  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.3 / Dec. 2009  
1

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