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HMP125U7EFR8C-S6 PDF预览

HMP125U7EFR8C-S6

更新时间: 2024-11-05 05:36:19
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器双倍数据速率
页数 文件大小 规格书
29页 262K
描述
1240pin DDR2 SDRAM Unbuffered DIMMs

HMP125U7EFR8C-S6 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.46访问模式:DUAL BANK PAGE BURST
最长访问时间:0.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):400 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N240长度:133.35 mm
内存密度:19327352832 bit内存集成电路类型:DDR DRAM
内存宽度:72功能数量:1
端口数量:1端子数量:240
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:55 °C
最低工作温度:组织:256MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM240,40
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.18 A
子类别:Other Memory ICs最大压摆率:2.475 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
Base Number Matches:1

HMP125U7EFR8C-S6 数据手册

 浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第2页浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第3页浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第4页浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第5页浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第6页浏览型号HMP125U7EFR8C-S6的Datasheet PDF文件第7页 
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb E version  
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2  
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb  
version E based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm  
width form factor of industry standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate2 Syn-  
chrnous DRAMs (DDR2 SDRAMs) with 1.8V +/  
- 0.1V Power Supply  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
All inputs and outputs are compatible with  
SSTL_1.8 interface  
Serial presence detect with EEPROM  
8 Bank architecture  
DDR2 SDRAM Package: 60ball  
FBGA(128Mx8),  
84ball FBGA(64Mx16)  
Posted CAS  
Programmable CAS Latency 3,4,5, 6  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
133.35 x 30.00 mm form factor  
RoHS compliant & Halogen-free  
Fully differential clock operations (CK & CK)  
ORDERING INFORMATION  
# of  
DRAMs  
# of  
ranks  
Part Name  
Density  
Org.  
Materials  
ECC  
HMP164U6EFR8C-C4/Y5/S6/S5  
HMP112U6EFR8C-C4/Y5/S6/S5  
HMP112U7EFR8C-C4/Y5/S6/S5  
HMP125U6EFR8C-C4/Y5/S6/S5  
HMP125U7EFR8C-C4/Y5/S6/S5  
512MB  
1GB  
64Mx64  
128Mx64  
128Mx72  
256Mx64  
256Mx72  
4
8
1
1
1
2
2
Halogen free None  
Halogen free None  
1GB  
9
Halogen free  
Halogen free None  
Halogen free ECC  
ECC  
2GB  
16  
18  
2GB  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.3 / Nov. 2008  
1

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