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HM5283206FP-10 PDF预览

HM5283206FP-10

更新时间: 2024-10-28 20:29:43
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟动态存储器内存集成电路
页数 文件大小 规格书
80页 874K
描述
IC,SDRAM,2X128KX32,CMOS,QFP,100PIN,PLASTIC

HM5283206FP-10 技术参数

生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
最长访问时间:10 ns最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PQFP-G100内存密度:8388608 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
端子数量:100字数:262144 words
字数代码:256000最高工作温度:70 °C
最低工作温度:组织:256KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
刷新周期:1024连续突发长度:1,2,4,8,FP
最大待机电流:0.003 A子类别:DRAMs
最大压摆率:0.24 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
Base Number Matches:1

HM5283206FP-10 数据手册

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HM5283206 Series  
8M LVTTL interface SGRAM  
125 MHz/100 MHz/83 MHz  
128-kword × 32-bit × 2-bank  
ADE-203-223F (Z)  
Rev. 6.0  
Oct. 2, 1998  
Description  
All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2  
banks to realize better performance. 8 column block write function and write per bit function are provided  
for graphic applications.  
Features  
3.3V Power supply  
Clock frequency: 125 MHz/100 MHz/83 MHz (max)  
LVTTL interface  
2 Banks can operates simultaneously and independently  
Burst read/write operation and burst read/ single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 1/2/3  
Byte control by DQM  
8 column block write function with column address mask  
Write per bit function (old mask)  
Refresh cycles: 1024 refresh cycle/16 ms  
2 variations of refresh  
Auto refresh  
Self refresh  

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