Datasheet > HM52Y64805FTT-75

HM52Y64805FTT-75

更新时间： 2024-10-28 20:35:47

品牌	Logo	应用领域
日立 - HITACHI		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
56页	1713K
描述
Synchronous DRAM, 8MX8, 5.5ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

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HM52Y64805FTT-75 数据手册

HM52Y64165F Series

HM52Y64805F Series

HM52Y64405F Series

64M SDRAM

133 MHz/125 MHz

1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank

/4-Mword × 4-bit × 4-bank

ADE-203-974 (Z)

Preliminary

Rev. 0.0

Oct. 30, 1998

Description

The Hitachi HM52Y64165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hita-

chi HM52Y64805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi

HM52Y64405F is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs

are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features

•

2.5 V power supply

Clock frequency: 133 MHz/125 MHz (max)

Single pulsed RAS

4 banks can operate simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8/full page

2 variations of burst sequence

— Sequential (BL = 1/2/4/8/full page)

— Interleave (BL = 1/2/4/8)

•

Programmable CAS latency: 2/3

Byte control by DQM:DQM (HM52Y64805F/HM52Y64405F)

: DQMU/DQML (HM52Y64165F)

Refresh cycles: 4096 refresh cycles/64 ms

2 variations of refresh

•

— Auto refresh

— Self refresh

•

Full page burst length capability

— Sequential burst

12 3 4 5 6 7...56

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