Datasheet > 存储 > DRAM> HM5212325FBPC-B60

HM5212325FBPC-B60

更新时间： 2024-10-26 22:18:07

品牌	Logo	应用领域
日立 - HITACHI		存储内存集成电路动态存储器 PC 时钟
页数	文件大小	规格书
13页	60K
描述
128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM

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HM5212325FBPC-B60 数据手册

HM5212325FBPC-B60

128M LVTTL interface SDRAM

100 MHz

1-Mword × 32-bit × 4-bank

PC/100 SDRAM

ADE-203-1122C (Z)

Rev. 1.0

May. 12 , 2000

Description

The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All

inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine

pitch BGA.

Features

•

Single chip wide bit solution (× 32)

3.3 V power supply

Clock frequency: 100 MHz (max)

LVTTL interface

Extremely small foot print: 0.8 mm pitch

Package: FBGA (BP-90)

•

4 banks can operate simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 4/8/full page

2 variations of burst sequence

Sequential (BL = 4/8/full page)

Interleave (BL = 4/8)

•

Programmable CAS latency: 2/3

Byte control by DQMB

Refresh cycles: 4096 refresh cycles/64 ms

12 3 4 5 6 7...13

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型号	品牌	获取价格	描述	数据表
HM5212805DLTD-A60	HITACHI	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
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HM5212805FLTD-75	HITACHI	获取价格	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-b
HM5212805FLTD-75	ELPIDA	获取价格	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-
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HM5212805FLTD-A60	ELPIDA	获取价格	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-
HM5212805FLTD-A60	HITACHI	获取价格	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-b
HM5212805FLTD-B60	HITACHI	获取价格	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-b