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HM5212805FLTD-75 PDF预览

HM5212805FLTD-75

更新时间: 2024-10-27 05:36:11
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器PC
页数 文件大小 规格书
62页 629K
描述
128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM

HM5212805FLTD-75 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.73访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0长度:22.22 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:54
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.22 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

HM5212805FLTD-75 数据手册

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HM5212165FLTD-75/A60/B60  
HM5212805FLTD-75/A60/B60  
128M LVTTL interface SDRAM  
133 MHz/100 MHz  
2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank  
PC/133, PC/100 SDRAM  
E0180H10 (Ver. 1.0)  
Jul. 17, 2001  
Description  
The HM5212165FL is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The  
HM5212805FL is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. Allinputs and outputs are  
referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 133 MHz/100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  
Byte control by DQM : DQM (HM5212805FL)  
: DQMU/DQML (HM5212165FL)  
Refresh cycles: 4096 refresh cycles/64 ms  
This product became EOL in June, 2005.  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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