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HM5212805DLTD-B60 PDF预览

HM5212805DLTD-B60

更新时间: 2024-10-27 19:45:55
品牌 Logo 应用领域
日立 - HITACHI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
63页 599K
描述
Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5212805DLTD-B60 数据手册

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HM5212165D-B60  
HM5212805D-B60  
128M LVTTL interface SDRAM  
100 MHz  
2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank  
PC/100 SDRAM  
ADE-203-953B (Z)  
Preliminary, Rev. 0.2  
Nov. 30, 1998  
Description  
The Hitachi HM5212165D is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The  
Hitachi HM5212805D is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and  
outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  

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128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-b