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HEF4081BT,652 PDF预览

HEF4081BT,652

更新时间: 2024-11-05 07:24:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
12页 127K
描述
HEF4081B - Quad 2-input AND gate SOIC 14-Pin

HEF4081BT,652 数据手册

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HEF4081B  
Quad 2-input AND gate  
Rev. 7 — 16 November 2011  
Product data sheet  
1. General description  
The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest  
noise immunity and pattern insensitivity to output impedance variations.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Inputs and outputs are protected against electrostatic effects  
Specified from40 C to +85 C and 40 C to +125 C  
Complies with JEDEC standard JESD 13-B  
3. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +125 C.  
Type number  
Package  
Name  
Description  
Version  
HEF4081BP  
HEF4081BT  
DIP14  
SO14  
plastic dual in-line package; 14 leads (300 mil)  
plastic small outline package; 14 leads; body width 3.9 mm  
SOT27-1  
SOT108-1  
4. Functional diagram  
1
2
1A  
1B  
1Y  
2Y  
3Y  
3
5
6
2A  
2B  
4
8
9
3A  
3B  
10  
12  
13  
4A  
4B  
4Y 11  
nA  
nB  
nY  
001aai139  
001aag180  
Fig 1. Functional diagram  
Fig 2. Logic diagram (one gate)  

HEF4081BT,652 替代型号

型号 品牌 替代类型 描述 数据表
HEF4081BT,653 NXP

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HEF4081B - Quad 2-input AND gate SOIC 14-Pin
MC14081BDR2G ONSEMI

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