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HEF4081BT-T PDF预览

HEF4081BT-T

更新时间: 2024-11-04 21:19:03
品牌 Logo 应用领域
恩智浦 - NXP 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
12页 127K
描述
IC 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Gate

HEF4081BT-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.15系列:4000/14000/40000
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):110 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

HEF4081BT-T 数据手册

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HEF4081B  
Quad 2-input AND gate  
Rev. 7 — 16 November 2011  
Product data sheet  
1. General description  
The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest  
noise immunity and pattern insensitivity to output impedance variations.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Inputs and outputs are protected against electrostatic effects  
Specified from40 C to +85 C and 40 C to +125 C  
Complies with JEDEC standard JESD 13-B  
3. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +125 C.  
Type number  
Package  
Name  
Description  
Version  
HEF4081BP  
HEF4081BT  
DIP14  
SO14  
plastic dual in-line package; 14 leads (300 mil)  
plastic small outline package; 14 leads; body width 3.9 mm  
SOT27-1  
SOT108-1  
4. Functional diagram  
1
2
1A  
1B  
1Y  
2Y  
3Y  
3
5
6
2A  
2B  
4
8
9
3A  
3B  
10  
12  
13  
4A  
4B  
4Y 11  
nA  
nB  
nY  
001aai139  
001aag180  
Fig 1. Functional diagram  
Fig 2. Logic diagram (one gate)  

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