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HEF4081BT-Q100 PDF预览

HEF4081BT-Q100

更新时间: 2024-11-05 11:14:43
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
9页 192K
描述
Quad 2-input AND gateProduction

HEF4081BT-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
系列:4000/14000/40000JESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
逻辑集成电路类型:AND GATE湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):110 ns筛选级别:AEC-Q100
座面最大高度:1.75 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

HEF4081BT-Q100 数据手册

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HEF4081B-Q100  
Quad 2-input AND gate  
Rev. 2 — 21 February 2022  
Product data sheet  
1. General description  
The HEF4081B-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the  
use of current limiting resistors to interface inputs to voltages in excess of VDD  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Inputs and outputs are protected against electrostatic effects  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Complies with JEDEC standard JESD 13-B  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range  
-40 °C to +125 °C  
Name  
Description  
Version  
HEF4081BT-Q100  
SO14  
plastic small outline package;  
14 leads; body width 3.9 mm  
SOT108-1  
4. Functional diagram  
1
2
1A  
1B  
1Y  
2Y  
3Y  
3
5
6
2A  
2B  
4
8
9
3A  
3B  
10  
12  
13  
4A  
4B  
4Y 11  
nA  
nB  
nY  
001aag180  
001aai139  
Fig. 1. Functional diagram  
Fig. 2. Logic diagram (one gate)  
 
 
 
 

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